ST STM32L4+ Series Reference Manual page 437

RM0432
13.5.7 DMA2D background offset register (DMA2D_BGOR)
Address offset: 0x0018
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 LO[15:0]: Line offset
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
rw rw rw rw
The line offset used for the background image, expressed in pixel when the LOM bit is
reset and in byte when the LOM bit is set.
When expressed in pixels, only LO[13:0] is considered, LO[15:14] are ignored.
This value is used for the address generation. It is added at the end of each line to
determine the starting address of the next line.
These bits can only be written when data transfers are disabled. Once data transfer has
started, they become read-only.
If the image format is 4-bit per pixel, the line offset must be even.
RM0432 Rev 6
Chrom-ART Accelerator controller (DMA2D)
23 22 21
Res. Res. Res.
7 6 5
LO[15:0]
rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2
rw rw rw rw
16
Res.
1 0
rw
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