ST STM32L4+ Series Reference Manual page 899

RM0432
Color look-up table (CLUT)
The CLUT can be enabled at run-time for every layer through the LTDC_LxCR register and
it is only useful in case of indexed color when using the L8, AL44 and AL88 input pixel
format.
First, the CLUT must be loaded with the R, G and B values that replace the original R, G, B
values of that pixel (indexed color). Each color (RGB value) has its own address that is the
position within the CLUT.
The R, G and B values and their own respective address are programmed through the
LTDC_LxCLUTWR register:
• In case of L8 and AL88 input pixel format, the CLUT must be loaded by 256 colors. The
address of each color is configured in the CLUTADD bits in the LTDC_LxCLUTWR
register.
• In case of AL44 input pixel format, the CLUT must be loaded by only16 colors. The
address of each color must be filled by replicating the 4-bit L channel to 8-bit as follows:
– L0 (indexed color 0), at address 0x00
– L1, at address 0x11
– L2, at address 0x22
– .....
– L15, at address 0xFF
Color frame buffer address
Every layer has a start address for the color frame buffer configured through the
LTDC_LxCFBAR register.
When a layer is enabled, the data is fetched from the color frame buffer.
Color frame buffer length
Every layer has a total line length setting for the color frame buffer in bytes and a number of
lines in the frame buffer configurable in the LTDC_LxCFBLR and LTDC_LxCFBLNR register
respectively.
The line length and the number of lines settings are used to stop the prefetching of data to
the layer FIFO at the end of the frame buffer:
• If it is set to less bytes than required, a FIFO underrun interrupt is generated if it has
been previously enabled.
•
If it is set to more bytes than actually required, the useless data read from the FIFO is
discarded. The useless data is not displayed.
Color frame buffer pitch
Every layer has a configurable pitch for the color frame buffer, that is the distance between
the start of one line and the beginning of the next line in bytes. It is configured through the
LTDC_LxCFBLR register.
RM0432 Rev 6
LCD-TFT display controller (LTDC)
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