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RM0432
Bits 31: 25 Reserved, must be kept at reset value
Bit 24 PM: Presp mode
Bits 23: 16 Reserved, must be kept at reset value
Bits 15: 0 HSWR_TOCNT: High-Speed Write Timeout Counter
30.15.31 DSI Host Timeout Counter Configuration Register 4 (DSI_TCCR4)
Address offset: 0x0088
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Bits 31: 16 Reserved, must be kept at reset value
Bits 15: 0 LSWR_TOCNT: Low-Power Write Timeout Counter
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
When set to 1, this bit ensures that the peripheral response timeout caused by
HSWR_TOCNT is used only once per LTDC frame in Command mode, when both the
following conditions are met:
– dpivsync_edpiwms has risen and fallen.
– Packets originated from LTDC in Command mode have been transmitted and its FIFO
is empty again.
In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is
traffic from generic interface ready to be sent, making it return to stop state. When it does
so, PRESP_TO counter is activated and only when it finishes does the controller send any
other traffic that is ready.
This field sets a period for which the DSI Host keeps the link inactive after sending a High-
Speed write operation. This period is measured in cycles of lanebyteclk. The counting
starts when the D-PHY enters the Stop state and causes no interrupts.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
This field sets a period for which the DSI Host keeps the link still, after sending a Low-
Power write operation. This period is measured in cycles of lanebyteclk. The counting
starts when the D-PHY enters the Stop state and causes no interrupts.
24
23
22
Res.
Res.
Res.
8
7
6
LPWR_TOCNT[15:0]
rw
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
17
16
Res.
Res.
1
0
1003/2301
1044
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