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RM0432
Bit 4 GPIOEEN: IO port E clock enable
Set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
Bit 3 GPIODEN: IO port D clock enable
Set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Bit 2 GPIOCEN: IO port C clock enable
Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 1 GPIOBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
6.4.18
AHB3 peripheral clock enable register(RCC_AHB3ENR)
Address offset: 0x50
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
Note:
When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 OSPI2EN: OctoSPI2 memory interface clock enable
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
OSPI2
Res.
Res.
Res.
EN
rw
Set and cleared by software.
0: OctoSPI2 clock disable
1: OctoSPI2 clock enable
24
23
22
Res.
Res.
Res.
8
7
6
OSPI1E
Res.
Res.
N
rw
RM0432 Rev 6
Reset and clock control (RCC)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
FMCE
Res.
N
rw
289/2301
320
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