ST STM32L4+ Series Reference Manual page 167

RM0432
3.7.18 FLASH register map
Offset Register
FLASH_ACR
0x00
Reset value
FLASH_
PDKEYR
0x04
Reset value 0
FLASH_KEYR
0x08
Reset value 0
FLASH_OPT
KEYR
0x0C
Reset value 0
FLASH_SR
0x10
Reset value
FLASH_CR
0x14
Reset value 1
FLASH_ECCR
0x18
Reset value 0
FLASH_OPTR
0x20
Reset value
FLASH_
PCROP1SR
0x24
Reset value
FLASH_
PCROP1ER
0x28
Reset value x
FLASH_
WRP1AR
0x2C
Reset value
Table 20. Flash interface - register map and reset values
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 0 0 0 0
0 0 0 0
X X X X X X X X X X X X
X X X X X X X X
0
PDKEYR[31:0]
0 0 0 0 0 0 0 0 0
KEYR[31:0]
0 0 0 0 0 0 0 0 0
OPTKEYR[31:0]
0 0 0 0 0 0 0 0 0
X 0 0 0
0 0 0 0
0 0 0 0 0 0 0 0 0
X X X
1 X X X X X X X X X X X X X X X X
0 X X X X X X X X X X X X X X X X
WRP1A_END[7:0]
RM0432 Rev 6
Embedded Flash memory (FLASH)
0 0 0 1 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0
PNB[7:0]
0 0 0 0 0 0
ADDR_ECC[20:0]
0 0 0 0 0 0 0 0
BOR_
LEV[2:0]
X X X X X X X X X X X
PCROP1_STRT[16:0]
PCROP1_END[16:0]
WRP1A_STRT[7:0]
X X X X X X X X
LATENCY
[3:0]
0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
RDP[7:0]
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