ST STM32L4+ Series Reference Manual page 312

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Reset and clock control (RCC)

Bit 4 LSIPREDIV: Internal low-speed oscillator predivided by 128

Note: This bit is available only on STM32L4P5xx and STM32L4Q5xx devices.

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 LSIRDY: LSI oscillator ready

Bit 0 LSION: LSI oscillator enable

Clock recovery RC register (RCC_CRRCR)

Address: 0x98

Reset value: 0x0000 XXX0 where X is factory-programmed.

Access: no wait state, word, half-word and byte access

Bits 31:16 Reserved, must be kept at reset value

Bits 15:7 HSI48CAL[8:0]: HSI48 clock calibration

Set and reset by software. This bit is used to enable the internal clock divider (/128) of the

LSI clock. The software has to disable the LSI (LSION=0 and LSIRDY=0) before to change

0: LSI PREDIV OFF

1: LSI PREDIV ON

Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit

is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if

LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent

Watchdog or by the RTC.

0: LSI oscillator not ready

1: LSI oscillator ready

Set and cleared by software.

0: LSI oscillator OFF

1: LSI oscillator ON

HSI48CAL[8:0]

These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.

They are ready only.

RM0432 Rev 6

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