ST STM32L4+ Series Reference Manual page 317

RM0432
Off-
Register
set
RCC_ PLLSAI1PDI
PLLSAI1
0x10
CFGR
0 0 0 0 0 0 0 0
Reset value
RCC_ PLLSAI2PDI
PLLSAI2
0x14
CFGR
0 0 0 0 0 0 0 0
Reset value
RCC_CIER
0x18
Reset value
RCC_CIFR
0x1C
Reset value
RCC_CICR
0x20
Reset value
RCC_
AHB1RSTR
0x28
Reset value
RCC_
AHB2RSTR
0x2C
Reset value
Table 38. RCC register map and reset values (continued)
PLL
SAI1
V
R
[4:0]
[1:0]
PLL
SAI2
R
V
[4:0]
[1:0]
0 0
PLL
SAI1
Q
[1:0]
0 0 0 0 0
0 0 0 0 0
0 0 0
0 0 0 0 0 0 0 0
RM0432 Rev 6
Reset and clock control (RCC)
PLLSAI1N
PLLSAI1M
[3:0]
[6:0]
0 0 1 0 0 0 0 0 0 0 0
PLLSAI2N
PLLSAI2M
[3:0]
[6:0]
0 0 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0 0
0 0 0
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