ST STM32L4+ Series Reference Manual page 838

Digital filter for sigma delta modulators (DFSDM)
Output clock generation
A clock signal can be provided on CKOUT pin to drive external Σ∆ modulator clock inputs.
The frequency of this CKOUT signal is derived from DFSDM clock or from audio clock (see
CKOUTSRC bit in DFSDM_CH0CFGR1 register) divided by a predivider (see CKOUTDIV
bits in DFSDM_CH0CFGR1 register). If the output clock is stopped, then CKOUT signal is
set to low state (output clock can be stopped by CKOUTDIV=0 in DFSDM_CHyCFGR1
register or by DFSDMEN=0 in DFSDM_CH0CFGR1 register). The output clock stopping is
performed:
•
4 system clocks after DFSDMEN is cleared (if CKOUTSRC=0)
•
1 system clock and 3 audio clocks after DFSDMEN is cleared (if CKOUTSRC=1)
Before changing CKOUTSRC the software has to wait for CKOUT being stopped to avoid
glitch on CKOUT pin. The output clock signal frequency must be in the range 0 - 20 MHz.
SPI data input format operation
In SPI format, the data stream is sent in serial format through data and clock signals. Data
signal is always provided from DATINy pin. A clock signal can be provided externally from
CKINy pin or internally from a signal derived from the CKOUT signal source.
In case of external clock source selection (SPICKSEL[1:0]=0) data signal (on DATINy pin) is
sampled on rising or falling clock edge (of CKINy pin) according SITP[1:0] bits setting (in
DFSDM_CHyCFGR1 register).
Internal clock sources - see SPICKSEL[1:0] in DFSDM_CHyCFGR1 register:
•
CKOUT signal:
–
–
•
CKOUT/2 signal (generated on CKOUT rising edge):
–
–
•
CKOUT/2 signal (generated on CKOUT falling edge):
–
–
Note: An internal clock source can only be used when the external Σ∆ modulator uses CKOUT
signal as a clock input (to have synchronous clock and data operation).
Internal clock source usage can save CKINy pin connection (CKINy pins can be used for
other purpose).
The clock source signal frequency must be in the range 0 - 20 MHz for SPI coding and less
than f
DFSDMCLK
Manchester coded data input format operation
In Manchester coded format, the data stream is sent in serial format through DATINy pin
only. Decoded data and clock signal are recovered from serial stream after Manchester
838/2301
For connection to external Σ∆ modulator which uses directly its clock input (from
CKOUT) to generate its output serial communication clock.
Sampling point: on rising/falling edge according SITP[1:0] setting.
For connection to external Σ∆ modulator which divides its clock input (from
CKOUT) by 2 to generate its output serial communication clock (and this output
clock change is active on each clock input rising edge).
Sampling point: on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from
CKOUT) by 2 to generate its output serial communication clock (and this output
clock change is active on each clock input falling edge).
Sampling point: on each second CKOUT rising edge.
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RM0432 Rev 6
RM0432