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DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
30.15.36 DSI Host PHY Control Register (DSI_PCTLR)
Address offset: 0x00A0
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31: 3 Reserved, must be kept at reset value
Bit 2 CKE: Clock Enable
Bit 1 DEN: Digital Enable
Bit 0 Reserved
30.15.37 DSI Host PHY Configuration Register (DSI_PCONFR)
Address offset: 0x00A4
Reset value: 0x0000 0001
31
30
29
Res.
Res.
Res.
Res.
15
14
13
SW_TIME[7:0]
Bits 31: 16 Reserved, must be kept at reset value
Bits 15: 8 SW_TIME: Stop Wait Time
1006/2301
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit enables the D-PHY Clock Lane module:
0: D-PHY Clock lane module is disabled.
1: D-PHY Clock lane module is enabled.
When set to 0, this bit places the digital section of the D-PHY in the reset state
0: The digital section of the D-PHY is in the reset state.
1: The digital section of the D-PHY is enabled.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
rw
This field configures the minimum wait period to request a High-Speed transmission after
the Stop state.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
CKE
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0432
17
16
Res.
Res.
1
0
DEN
Res.
rw
17
16
Res.
Res.
1
0
NL[1:0]
rw
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