ST STM32L4+ Series Reference Manual page 109

RM0432
The write protection can be enabled in
(SYSCFG_SWPR)
which means by writing '1' on a bit it will setup the write protection for that page of SRAM
and it can be removed/cleared by a system reset only.
2.4.3 SRAM2 Read protection
The SRAM2 is protected with the Read protection (RDP). Refer to
protection (RDP)
2.4.4 SRAM2 Erase
The SRAM2 can be erased with a system reset using the option bit SRAM2_RST in the user
option byte (refer to
The SRAM2 erase can also be requested by software by setting the bit SRAM2ER in the
SYSCFG SRAM2 control and status register
2.5 Flash memory overview
The Flash memory is composed of two distinct physical areas:
•
The main Flash memory block. It contains the application program and user data if
necessary.
•
The information block. It is composed of three parts:
–
–
–
The Flash interface implements instruction access and data access based on the AHB
protocol. It also implements the logic necessary to carry out the Flash memory operations
Table 3. SRAM2 organization (continued)
Page number
Page 53
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in the SYSCFG block. This is a register with write '1' once mechanism,
for more details.
Section 3.4.1: Option bytes
Option bytes for hardware and memory protection user configuration.
System memory that contains the ST proprietary code.
OTP (one-time programmable) area
Start address
0x1000 D400
0x1000 D800
0x1000 DC00
0x1000 E000
0x1000 E400
0x1000 E800
0x1000 EC00
0x1000 F000
0x1000 F400
0x1000 F800
0x1000 FC00
SYSCFG SRAM2 write protection register
description).
(SYSCFG_SCSR).
RM0432 Rev 6
End address
0x1000 D7FF
0x1000 DBFF
0x1000 DFFF
0x1000 E3FF
0x1000 E7FF
0x1000 EBFF
0x1000 EFFF
0x1000 F3FF
0x1000 F7FF
0x1000 FBFF
0x1000 FFFF
Section 3.5.1: Read
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