ST STM32L4+ Series Reference Manual page 298

Reset and clock control (RCC)
Bit 18 RNGSMEN: Random Number Generator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Random Number Generator clocks disabled by the clock gating during Sleep and Stop
modes
1: Random Number Generator clocks enabled by the clock gating during Sleep and Stop
modes
Bit 17 HASHSMEN: HASH clock enable during Sleep and Stop modes
Set and cleared by software
0: HASH clocks disabled by the clock gating
1: HASH clocks enabled by the clock gating
Bit 16 AESSMEN: AES accelerator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: AES clocks disabled by the clock gating
1: AES clocks enabled by the clock gating
Bit 15 PKASMEN: PKA clocks enable during Sleep and Stop modes
Set and cleared by software.
0: PKA clocks disabled by the clock gating
1: PKA clocks enabled by the clock gating
Bit 14 DCMISMEN: DCMI or PSSI clock enable during Sleep and Stop modes. (DCMI or PSSI
depending on which interface is active)
Set and cleared by software
0: DCMI/PSSI clocks disabled by the clock gating
1: DCMI/PSSI clocks enabled by the clock gating
Bit 13 ADCSMEN: ADC clocks enable during Sleep and Stop modes
Set and cleared by software.
0: ADC clocks disabled by the clock gating
1: ADC clocks enabled by the clock gating
Bit 12 OTGFSSMEN: OTG full speed clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USB OTG full speed clocks disabled by the clock gating
1: USB OTG full speed clocks enabled by the clock gating
Bits 11 Reserved, must be kept at reset value.
Bit 10 SRAM3SMEN: SRAM2 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SRAM3 interface clocks disabled by the clock gating
1: SRAM3 interface clocks enabled by the clock gating
Bit 9 SRAM2SMEN: SRAM2 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SRAM2 interface clocks disabled by the clock gating
1: SRAM2 interface clocks enabled by the clock gating
Bit 8 GPIOISMEN: IO port I clocks enable during Sleep and Stop modes
Set and cleared by software
0: IO port I clocks disabled by the clock gating
1: IO port I clocks enabled by the clock gating
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RM0432 Rev 6
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RM0432