ST STM32L4+ Series Reference Manual page 680

Analog-to-digital converters (ADC)
Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences
with the same length or ensure that the interval between triggers is longer than the long
conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may
restart while the ADC with the longest sequence is completing the previous conversions.
ADC MASTER reg
ADC MASTER inj
ADC SLAVE reg
ADC SLAVE inj
If a trigger occurs during an injected conversion that has interrupted a regular conversion,
the alternate trigger is served.
trigger is ignored because the associated alternate conversion is not complete).
Figure 148. Case of trigger occurring during injected conversion
ADC MASTER reg
CH1
ADC MASTER inj
ADC SLAVE reg
ADC SLAVE inj
Combined injected simultaneous plus interleaved
This mode is selected by programming bits DUAL[4:0]=00011
It is possible to interrupt an interleaved conversion with a simultaneous injected event.
In this case the interleaved conversion is interrupted immediately and the simultaneous
injected conversion starts. At the end of the injected sequence the interleaved conversion is
resumed. When the interleaved regular conversion resumes, the first regular conversion
which is performed is alway the master's one.
the behavior using an example.
Caution: In this mode, it is mandatory to use the Common Data Register to read the regular data with
a single read access. On the contrary, master-slave data coherency is not guaranteed.
680/2301
Figure 147. Alternate + regular simultaneous
1st trigger
CH1 CH2
CH4 CH6
1st trigger
CH2 CH3
CH14
CH7 CH8 CH9
CH15
2nd trigger
CH3 CH3
CH1
CH7 CH7
Figure 148 shows the behavior in this case (note that the 6th
3rd trigger
CH3 CH4
CH14
CH9 CH10
Figure
RM0432 Rev 6
CH4 CH4
CH8 CH8
CH1
synchro not lost
2nd trigger
5th trigger
CH5
CH4
CH14
CH11
CH10
CH15
6th trigger
(ignored)
4th trigger
149, Figure 150 and Figure 151
RM0432
CH5
CH9
ai16062V2-m
CH5 CH6
CH11 CH12
ai16063V2
show