ST STM32L4+ Series Reference Manual page 493

RM0432
17.4 CRC registers
17.4.1 CRC data register (CRC_DR)
Address offset: 0x00
Reset value: 0xFFFF FFFF
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 DR[31:0]: Data register bits
17.4.2 CRC independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits
These bits can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the
correct value.
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
Cyclic redundancy check calculation unit (CRC)
24 23 22
DR[31:16]
rw rw rw
8 7 6
DR[15:0]
rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
Res.
RM0432 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
IDR[7:0]
rw
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
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