ST STM32L4+ Series Reference Manual page 997

RM0432
30.15.23 DSI Host Command mode Configuration Register (DSI_CMCR)
Address offset: 0x0068
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
GSR
GSR
Res. GLWTX
2TX
rw rw
Bits 31: 25 Reserved, must be kept at reset value
Bit 24 MRDPS: Maximum Read Packet Size
Bits 23: 20 Reserved, must be kept at reset value
Bit 19 DLWTX: DCS Long Write Transmission
Bit 18 DSR0TX: DCS Short Read Zero parameter Transmission
Bit 17 DSW1TX: DCS Short Read One parameter Transmission
Bit 16 DSW0TX: DCS Short Write Zero parameter Transmission
Bit 15 Reserved, must be kept at reset value
Bit 14 GLWTX: Generic Long Write Transmission
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
28 27 26 25
Res. Res. Res.
12 11 10 9
GSR GSW GSW
0TX 2TX 1TX
1TX
rw rw rw rw
This bit configures the maximum read packet size command transmission type:
0: High-speed.
1: Low-power.
This bit configures the DCS long write packet command transmission type:
0: High-speed.
1: Low-power.
This bit configures the DCS short read packet with zero parameter command transmission
type:
0: High-speed.
1: Low-power.
This bit configures the DCS short read packet with one parameter command transmission
type:
0: High-speed.
1: Low-power.
This bit configures the DCS short write packet with zero parameter command
transmission type:
0: High-speed.
1: Low-power.
This bit configures the Generic long write packet command transmission type :
0: High-speed.
1: Low-power.
24 23 22 21
MRDPS Res. Res. Res.
rw
8 7 6 5
GSW
Res. Res. Res.
0TX
rw
RM0432 Rev 6
20 19 18
Res. DLWTX DSR0TX DSW1TX DSW0TX
rw rw
4 3 2
Res. Res. Res. ARE
17 16
rw rw
1 0
TEARE
rw rw
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