ST STM32L4+ Series Reference Manual page 648

Analog-to-digital converters (ADC)
21.4.25 Timing diagrams example (single/continuous modes,
hardware/software triggers)
Figure 113. Single conversions of a sequence, software trigger
ADSTART (1)
EOC
EOS
RDY
ADC state (2)
ADC_DR
by s/w
1. EXTEN[1:0]=00, CONT=0
2. Channels selected = 1,9, 10, 17; AUTDLY=0.
Figure 114. Continuous conversion of a sequence, software trigger
(1)
ADSTART
EOC
EOS
ADSTP
(2)
ADC state READY CH1
ADC_DR
by s/w
1. EXTEN[1:0]=00, CONT=1
2. Channels selected = 1,9, 10, 17; AUTDLY=0.
648/2301
CH1 CH9 CH10 CH17
D1
D9
by h/w
CH9 CH10 CH17
D1 D9 D10
by h/w
RDY
CH1
D17
D10
CH1
CH9 CH10
D17 D1
RM0432 Rev 6
CH9 CH10 CH17
D1 D9 D10
Indicative timings
CH1
STP READY
D9
Indicative timings
RM0432
RDY
D17
MS30549V1
CH9
D1
MS30550V1