ST STM32L4+ Series Reference Manual page 930

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
The LTDC interface can be configured to increase flexibility and promote correct use of this
interface for several systems. The following configuration options are available:
•
Polarity control: All the control signals are programmable to change the polarity
depending on the LTDC configuration.
• After the core reset, DSI Host waits for the first VSYNC active transition to start signal
sampling, including pixel data, thus avoiding starting the transmission of the image data
in the middle of a frame.
•
If interface pixel color coding is 18 bits and the 18-bit loosely packed stream is
disabled, the number of pixels programmed in the VPSIZE field must be a multiple of
four. This means that in this mode, the two LSBs in the configuration are always
inferred as zero. The specification states that in this mode, the pixel line size should be
a multiple of four.
•
To avoid FIFO underflows and overflows, the configured number of pixels is assumed
to be received from the LTDC at all times.
•
To keep the memory organized with respect to the packet scheduling, the number of
pixels per packet parameter is used to separate the memory space of different video
packets.
For SHTDN and COLM sampling and transmission, the video streaming from the LTDC
must be active. This means that if the LTDC is not actively generating the video signals like
VSYNC and HSYNC, these signals are not transmitted through the DSI link. Because of
such constraints and for commands to be correctly transmitted, the first VSYNC active pulse
should occur for the command sampling and transmission. When shutting down the display,
it is necessary for the LTDC to be kept active for one frame after the command being issued.
This ensures that the commands are correctly transmitted before actually disabling the
video generation at the LTDC interface.
The SHTDN and COLM values can be programmed in the DSI Wrapper Control Register
(DSI_WCR).
For all of the data types, one entire pixel is received per each clock cycle. The number of
pixels of payload is restricted to a multiple of a value, as shown in
30.5.1 Video transmission mode
There are different video transmission modes, namely:
•
Burst mode
• Non-Burst mode
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Table 199. Multiplicity of the payload size in pixels for each data type
Value
1
2
4
Non-Burst mode with sync pulse
Non-Burst mode with sync event.
16-bit
18-bit loosely packed
24-bit
Loosely packed pixel stream
18-bit non-loosely packed
RM0432 Rev 6
Table 199.
Data Types
RM0432