ST STM32L4+ Series Reference Manual page 835

RM0432
dfsdm_jtrg24
dfsdm_jtrg25
dfsdm_jtrg26
dfsdm_jtrg[31:27]
dfsdm_break[0]
dfsdm_break[1]
dfsdm_break[2]
dfsdm_break[3]
28.4.3 DFSDM reset and clocks
DFSDM on-off control
The DFSDM interface is globally enabled by setting DFSDMEN=1 in the
DFSDM_CH0CFGR1 register. Once DFSDM is globally enabled, all input channels (y=0..7)
and digital filters DFSDM_FLTx (x=0..3) start to work if their enable bits are set (channel
enable bit CHEN in DFSDM_CHyCFGR1 and DFSDM_FLTx enable bit DFEN in
DFSDM_FLTxCR1).
Digital filter x DFSDM_FLTx (x=0..3) is enabled by setting DFEN=1 in the
DFSDM_FLTxCR1 register. Once DFSDM_FLTx is enabled (DFEN=1), both Sinc
filter unit and integrator unit are reinitialized.
By clearing DFEN, any conversion which may be in progress is immediately stopped and
DFSDM_FLTx is put into stop mode. All register settings remain unchanged except
DFSDM_FLTxAWSR and DFSDM_FLTxISR (which are reset).
Channel y (y=0..7) is enabled by setting CHEN=1 in the DFSDM_CHyCFGR1 register.
Once the channel is enabled, it receives serial data from the external Σ∆ modulator or
parallel internal data sources (ADCs or CPU/DMA wire from memory).
DFSDM must be globally disabled (by DFSDMEN=0 in DFSDM_CH0CFGR1) before
stopping the system clock to enter in the STOP mode of the device.
Table 186. DFSDM triggers connection (continued)
Trigger name
Table 187. DFSDM break connection
Break name
RM0432 Rev 6
Digital filter for sigma delta modulators (DFSDM)
EXTI11
EXTI15
LTIMER1
Reserved
Break destination
TIM1/TIM15 break
TIM1 break2 / TIM16 break
TIM8/TIM17 break
TIM8 break2
Trigger source
x
digital
835/2301
889