ST STM32L4+ Series Reference Manual page 136

Embedded Flash memory (FLASH)
PCROP1 Start address option bytes
Flash memory address: 0x1FF0 0008
ST production value: 0xFFFF FFFF
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:17 Reserved, must be kept at reset value.
PCROP1 End address option bytes
Flash memory address: 0x1FF0 0010
ST production value: 0x0000 0000
31 30 29
PCROP
Res. Res.
_RDP
rw
15 14 13
rw rw rw
136/2301
Bit 11 Reserved, must be kept at reset value.
Bits10:8 BOR_LEV: BOR reset Level
These bits contain the VDD supply level threshold that activates/releases the
reset.
000: BOR Level 0. Reset level threshold is around 1.7 V
001: BOR Level 1. Reset level threshold is around 2.0 V
010: BOR Level 2. Reset level threshold is around 2.2 V
011: BOR Level 3. Reset level threshold is around 2.5 V
100: BOR Level 4. Reset level threshold is around 2.8 V
Bits 7:0 RDP: Read protection level
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, memories read protection active
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
Bits 16:0 PCROP1_STRT[16:0]: PCROP area start offset
DBANK=1
PCROP1_STRT contains the first double-word of the PCROP area for bank1.
DBANK=0
PCROP1_STRT contains the first 2xdouble-word of the PCROP area for all
memory.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
PCROP1_STRT[16:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
PCROP1_END[16:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
RM0432
17 16
PCROP
Res. 1_STRT
[16:0]
rw
1 0
rw rw
17 16
PCRO
Res. P1_EN
D
rw
1 0
rw rw