ST STM32L4+ Series Reference Manual page 265

RM0432
Bits 22:21 PLLQ[1:0]: Main PLL division factor for PLL48M1CLK (48 MHz clock).
Caution:
Bit 20 PLLQEN: Main PLL PLL48M1CLK output enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 PLLP: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) or SDMMC clock.
Caution:
Bit 16 PLLPEN: Main PLL PLLSAI3CLK output enable
Bit 15 Reserved, must be kept at reset value.
Set and cleared by software to control the frequency of the main PLL output clock
PLL48M1CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These
bits can be written only if PLL is disabled.
PLL48M1CLK output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8
00: PLLQ = 2
01: PLLQ = 4
10: PLLQ = 6
11: PLLQ = 8
The software has to set these bits correctly not to exceed 120 MHz on
this domain.
Set and reset by software to enable the PLL48M1CLK output of the main PLL.
In order to save power, when the PLL48M1CLK output of the PLL is not used, the value of
PLLQEN should be 0.
0: PLL48M1CLK output disable
1: PLL48M1CLK output enable
Set and cleared by software to control the frequency of the main PLL output clock
PLLSAI3CLK. This output can be selected for SAI1 or SAI2 or SDMMC. These bits can be
written only if PLL is disabled.
When the PLLPDIV[4:0] is set to "00000"PLLSAI3CLK output clock frequency = VCO
frequency / PLLP with PLLP =7, or 17
0: PLLP = 7
1: PLLP = 17
The software has to set these bits correctly not to exceed 120 MHz on
this domain.
Set and reset by software to enable the PLLSAI3CLK output of the main PLL.
In order to save power, when the PLLSAI3CLK output of the PLL is not used, the value of
PLLPEN should be 0.
0: PLLSAI3CLK output disable
1: PLLSAI3CLK output enable
RM0432 Rev 6
Reset and clock control (RCC)
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