ST STM32L4+ Series Reference Manual page 560

Octo-SPI interface (OCTOSPI)
8 bits at a time (over IO0 to IO7 in Octal SPI mode). This can be configured using the
ADMODE[2:0] field of the OCTOSPI_CCR register.
The address can be sent in DTR mode (on each rising and falling edge of the clock) setting
the ADDTR bit in OCTOSPI_CCR.
When ADMODE[2:0] = 000, the address phase is skipped and the command sequence
proceeds directly to the next phase, if any.
In Memory-mapped mode, the address format for the write operation is specified in the
OCTOSPI_WCCR register. The address format for the read operation is specified in the
regular register OCTOSPI_CCR.
Alternate-bytes phase
In the alternate-bytes phase, 1 to 4 bytes are sent to the external device, generally to control
the mode of operation. The number of alternate bytes to be sent is configured in the
ABSIZE[1:0] field of the OCTOSPI_CCR register. The bytes to be sent are specified in the
OCTOSPI_ABR register.
The alternate-bytes phase can send 1 bit at a time (over SO in Single-SPI mode), 2 bits at a
time (over IO0 and IO1 in Dual-SPI mode), 4 bits at a time (over IO0 to IO3 in Quad-SPI
mode) or 8 bits at a time (over IO0 to IO7 in Octal SPI mode). This can be configured using
the ABMODE[2:0] field of the OCTOSPI_CCR register.
The alternate bytes can be sent in DTR mode (on each rising and falling edge of the clock)
setting the ABDTR bit of OCTOSPI_CCR.
When ABMODE[2:0] = 000, the alternate-bytes phase is skipped and the command
sequence proceeds directly to the next phase, if any.
There may be times when only a single nibble needs to be sent during the alternate-byte
phase rather than a full byte, such as when the Dual-SPI mode is used and only two cycles
are used for the alternate bytes.
In this case, the firmware can use the Quad-SPI mode (ABMODE[2:0] = 011) and send a
byte with bits 7 and 3 of ALTERNATE[31:0] set to 1 (keeping the IO3 line high), and bits 6
and 2 set to 0 (keeping the IO2 line low), in the OCSTOSPI_IR register.
The upper two bits of the nibble to be sent are then placed in bits 4:3 of ALTERNATE[31:0]
while the lower two bits are placed in bits 1 and 0. For example, if the nibble 2 (0010) is to be
sent over IO0/IO1, then ALTERNATE[31:0] must be set to 0x8A (1000_1010).
In Memory-mapped mode, the alternate bytes used for the write operation are specified in
the OCTOSPI_WABR register and the alternate byte format is specified in the
OCTOSPI_WCCR register. The alternate bytes used for read operation and the alternate
byte format are specified in the regular registers OCTOSPI_ABR and OCTOSPI_CCR.
Dummy-cycles phase
In the dummy-cycles phase, 1 to 31 cycles are given without any data being sent or
received, in order to give the external device, the time to prepare for the data phase when
the higher clock frequencies are used. The number of cycles given during this phase is
specified in the DCYC[4:0] field of the OCTOSPI_TCR register. In both SDR and DTR
modes, the duration is specified as a number of full CLK cycles.
When DCYC[4:0] = 00000, the dummy-cycles phase is skipped, and the command
sequence proceeds directly to the data phase, if present.
560/2301 RM0432 Rev 6
RM0432