ST STM32L4+ Series Reference Manual page 919

RM0432
Bits 12:0 CFBLL[12:0]: color frame buffer line length
These bits define the length of one line of pixels in bytes + 3.
The line length is computed as follows:
active high width * number of bytes per pixel + 3.
Example:
•
A frame buffer having the format RGB565 (2 bytes per pixel) and a width of 256 pixels
(total number of bytes per line is 256 * 2 = 512), where pitch = line length requires a
value of 0x02000203 to be written into this register.
•
A frame buffer having the format RGB888 (3 bytes per pixel) and a width of 320 pixels
(total number of bytes per line is 320 * 3 = 960), where pitch = line length requires a
value of 0x03C003C3 to be written into this register.
29.8.24 LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR)
This register defines the number of lines in the color frame buffer.
Address offset: 0xB4 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:11 Reserved, must be kept at reset value.
Bits 10:0 CFBLNBR[10:0]: frame buffer line number
These bits define the number of lines in the frame buffer that corresponds to the active high
width.
Note: The number of lines and line length settings define how much data is fetched per frame for
every layer. If it is configured to less bytes than required, a FIFO underrun interrupt will be
generated if enabled.
The start address and pitch settings on the other hand define the correct start of every line in
memory.
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res.
rw rw rw
RM0432 Rev 6
LCD-TFT display controller (LTDC)
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
CFBLNBR[10:0]
rw rw rw rw
19 18 17 16
Res. Res. Res. Res.
3 2 1
rw rw rw
919/2301
0
rw
923