ST STM32L4+ Series Reference Manual page 833

RM0432
28.4 DFSDM functional description
28.4.1 DFSDM block diagram
ADC 0
ADC 7
Parallel input data
register 0
EXTRG[1:0]
CKOUT
DATIN0
CKIN0
DATIN7
CKIN7
Control unit
Configuration
registers
DMA, interrupt, break
control, clock control
1. This example shows 4 DFSDM filters and 8 input channels (max. configuration).
Figure 191. Single DFSDM block diagram
APB bus
Sample 1 Sample 0
Sample 1 Sample 0
Parallel input data
register 7
Clock Mode
Pulse
control control
skipper
Serial transceiver 0
Mode
Clock
Pulse
control
control
skipper
Serial transceiver 7
Interrupt,
break
1's, 0's counter
threshold
Short circuit
detector 0 1's, 0's counter
threshold
Short circuit
detector 7
Digital filter for sigma delta modulators (DFSDM)
16
16
Data 0
Filter
Clock 0
order
16
Sinc
Data 3
Clock 3
16
8 watchdog filters
8 watchdog comparators
High threshold
Filter 0 Low threshold
config
Analog watchdog 0
High threshold
Filter 3 Low threshold
config
Analog watchdog 3
Maximum value
Minimum value
Extremes
Interrupts and events:
detector 0
1) end of conversion
2) analog watchdog
3) short circuit detection
4) overrun
RM0432 Rev 6
Oversampling Oversampling
ratio ratio
x
filter 0 Integrator unit 0
Filter Oversampling Oversampling
order ratio
x
Sinc filter 3 Integrator unit 3
Right bit-shift
count
Right bit-shift
Calibration data
count
correction unit
Interrupt,
Calibration data
break
DFSDM data 0
correction unit
DFSDM data 3
APB bus
Maximum value
Minimum value
Extremes
detector 3
ratio
Data output
MSv43818V2
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