ST STM32L4+ Series Reference Manual page 386

Direct memory access controller (DMA)
11.5 DMA interrupts
An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x. Separate interrupt enable bits are available for flexibility.
Interrupt request
Half transfer on channel x
Transfer complete on channel x
Channel x interrupt
Transfer error on channel x
Half transfer or transfer complete or transfer error on channel x
11.6 DMA registers
Refer to
The DMA registers have to be accessed by words (32-bit).
11.6.1 DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the DMA_IFCR register.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
TEIF4 HTIF4 TCIF4 GIF4
r r r
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 TEIF7: transfer error (TE) flag for channel 7
0: no TE event
1: a TE event occurred
Bit 26 HTIF7: half transfer (HT) flag for channel 7
0: no HT event
1: a HT event occurred
Bit 25 TCIF7: transfer complete (TC) flag for channel 7
0: no TC event
1: a TC event occurred
Bit 24 GIF7: global interrupt flag for channel 7
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
386/2301
Table 51. DMA interrupt requests
Interrupt event
Section 1.2 for a list of abbreviations used in register descriptions.
27 26 25
TEIF7 HTIF7 TCIF7
r r r
11 10 9
TEIF3 HTIF3 TCIF3
r r r r
24 23 22
GIF7 TEIF6 HTIF6 TCIF6
r r r
8 7 6
GIF3 TEIF2 HTIF2 TCIF2
r r r
RM0432 Rev 6
Event flag
HTIFx
TCIFx
TEIFx
GIFx
21 20 19 18
GIF6 TEIF5 HTIF5
r r r r
5 4 3 2
GIF2 TEIF1 HTIF1
r r r r
RM0432
Interrupt
enable bit
HTIEx
TCIEx
TEIEx
-
17 16
TCIF5 GIF5
r r
1 0
TCIF1 GIF1
r r