ST STM32L4+ Series Reference Manual page 418

Chrom-ART Accelerator controller (DMA2D)
FG PFC
Color mode
FG
Expander Expander
FIFO
CLUT itf
256x32-bit
BG PFC
Color mode
BG
Expander Expander
FIFO
CLUT itf
256x32-bit
RAM
13.3.2 DMA2D control
The DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR)
which allows selecting:
The user application can perform the following operations:
•
Select the operating mode
• Enable/disable the DMA2D interrupt
•
Start/suspend/abort ongoing data transfers
13.3.3 DMA2D foreground and background FIFOs
The DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to
be copied and/or processed.
The FIFOs fetch the pixels according to the color format defined in their respective pixel
format converter (PFC).
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Figure 35. DMA2D block diagram
D mode
8-bit D
32
D 8
32 RGB
RAM
D mode
8-bit D
32
D 8
32 RGB
D 32
X
BLENDER
D
32
Red
Green
32
Blue
D 32
X
RM0432 Rev 6
RM0432
AHB MASTER
OUT PFC
Color
Color mode
32
OUT
Converter
FIFO
32/24/16
AHB SLAVE
MS30439V1