ST STM32L4+ Series Reference Manual page 271

RM0432
Bits 22:21 PLLSAI2Q[1:0]: PLLSAI2 PLLDSICLK output enable.
Bit 20 PLLSAI2QEN: PLLSAI2 division factor for PLLDSICLK (DSI clock).
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 PLLSAI2P: PLLSAI2 division factor for PLLSAI2CLK (SAI1 or SAI2 clock).
Bit 16 PLLSAI2PEN: PLLSAI2 PLLSAI2CLK output enable
Bit 15 Reserved, must be kept at reset value.
Set and cleared by software to control the frequency of the DSI clock.
These bits can be written only if PLLSAI2 is disabled.
PLLDSICLK output clock frequency = VCOSAI2 frequency / PLLSAI2Q with PLLSAI2Q = 2,
4, 6, or 8
00: PLLSAI2Q = 2
01: PLLSAI2Q = 4
10: PLLSAI2Q = 6
11: PLLSAI2Q = 8
Set and reset by software to enable the PLLDSICLK (DSI clock) output of the PLLSAI2
(used as USB clock).
In order to save power, when the PLLDSICLK output of the PLLSAI2 is not used, the value of
PLLSAI2PEN should be 0.
0: PLLDSICLK output disable
1: PLLDSICLK output enable
Set and cleared by software to control the frequency of the PLLSAI2 output clock
PLLSAI2CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if
PLLSAI2 is disabled.
(when the PLLSAI2PDIV[4:0] is set to "00000"), PLLSAI2CLK output clock frequency =
VCOSAI2 frequency / PLLSAI2P with PLLSAI2P =7, or 17
0: PLLSAI2P = 7
1: PLLSAI2P = 17
Set and reset by software to enable the PLLSAI2CLK output of the PLLSAI2.
In order to save power, when the PLLSAI2CLK output of the PLLSAI2 is not used, the value
of PLLSAI2PEN should be 0.
0: PLLSAI2CLK output disable
1: PLLSAI2CLK output enable
RM0432 Rev 6
Reset and clock control (RCC)
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