ST STM32L4+ Series Reference Manual page 766

Digital camera interface (DCMI)
24 Digital camera interface (DCMI)
24.1 Introduction
The digital camera is a synchronous parallel interface able to receive a high-speed data flow
from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data
formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
24.2 DCMI main features
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8-, 10-, 12- or 14-bit parallel interface
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Embedded/external line and frame synchronization
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Continuous or snapshot mode
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Crop feature
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Supports the following data formats:
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24.3 DCMI functional description
The digital camera interface is a synchronous parallel interface that can receive high-speed
data flows. It consists of up to 14 data lines (DCMI_D[13:0]) and a pixel clock line
(DCMI_PIXCLK). The pixel clock has a programmable polarity, so that data can be captured
on either the rising or the falling edge of the pixel clock.
The data are packed into a 32-bit data register (DCMI_DR) and then transferred through a
general-purpose DMA channel. The image buffer is managed by the DMA, not by the
camera interface.
The data received from the camera can be organized in lines/frames (raw YUB/RGB/Bayer
modes) or can be a sequence of JPEG images. To enable JPEG image reception, the JPEG
bit (bit 3 of DCMI_CR register) must be set.
The data flow is synchronized either by hardware using the optional DCMI_HSYNC
(horizontal synchronization) and DCMI_VSYNC (vertical synchronization) signals or by
synchronization codes embedded in the data flow.
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8/10/12/14-bit progressive video: either monochrome or raw Bayer
YCbCr 4:2:2 progressive video
RGB 565 progressive video
Compressed data: JPEG
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