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Extended interrupts and events controller (EXTI)
16.5.8
Event mask register 2 (EXTI_EMR2)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value
16.5.9
Rising trigger selection register 2 (EXTI_RTSR2)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a rising edge on a configurable interrupt line occurs during a write operation to the
EXTI_RTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
486/2301
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bits 8:0 EMx: Event mask on line x (x = 40 to 32)
0: Event request from line x is masked
1: Event request from line x is not masked
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bits 7:3 RTx: Rising trigger event configuration bit of line x (x = 35 to 38)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Bits 2:0 Reserved, must be kept at reset value.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
EM40
EM39
EM38
EM37
rw
rw
rw
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
RT38
RT37
rw
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
5
4
3
2
EM36
EM35
EM34
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
5
4
3
2
RT36
RT35
Res.
rw
rw
rw
RM0432
17
16
Res.
Res.
1
0
EM33
EM32
rw
rw
17
16
Res.
Res.
1
0
Res.
Res.
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