ST STM32L4+ Series Reference Manual page 517

RM0432
Bit number
5:4
3:2
1
0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Table 101. FMC_BCRx bitfields (mode C) (continued)
Bit name
MWID As needed
MTYP 0x02 (NOR Flash memory)
MUXEN 0x0
MBKEN 0x1
Table 102. FMC_BTRx bitfields (mode C)
Bit name
Duration of the data hold phase (DATAHLD HCLK cycles for read
DATAHLD
accesses).
ACCMOD 0x2
DATLAT 0x0
CLKDIV 0x0
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for
DATAST
read accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for read
ADDSET
accesses. Minimum value for ADDSET is 0.
Table 103. FMC_BWTRx bitfields (mode C)
Bit name
Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
DATAHLD
accesses).
ACCMOD 0x2
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for
DATAST
write accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for write
ADDSET
accesses. Minimum value for ADDSET is 0.
RM0432 Rev 6
Flexible static memory controller (FSMC)
Value to set
Value to set
Value to set
517/2301
554