ST STM32L4+ Series Reference Manual page 105

RM0432
Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary
Bus Boundary address
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
APB1
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 1800 - 0x4000 23FF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00- 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
2.3 Bit banding
The Cortex
each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a
word in the alias region has the same effect as a read-modify-write operation on the
targeted bit in the bit-band region.
In the STM32L4+ Series devices both the peripheral registers and the SRAM1 are mapped
to a bit-band region, so that single bit-band write and read operations are allowed. The
operations are only available for Cortex
masters (such as DMA).
addresses (continued)
Size
(bytes)
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
4 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
®
-M4 with FPU memory map includes two bit-band regions. These regions map
RM0432 Rev 6
Peripheral
Section 50.7.15: USART register
USART3
map
Section 50.7.15: USART register
USART2
map
Reserved
SPI3 Section 52.6.8: SPI register map
SPI2 Section 52.6.8: SPI register map
TAMPER and
Section 48.6.9: TAMP register map
BKP registers
IWDG Section 44.4.6: IWDG register map
WWDG Section 45.5.4: WWDG register map
RTC Section 47.6.23: RTC register map
Reserved
TIM7 Section 40.4.9: TIMx register map
TIM6 Section 40.4.9: TIMx register map
TIM5 Section 38.4.26: TIMx register map
TIM4 Section 38.4.26: TIMx register map
TIM3 Section 38.4.26: TIMx register map
TIM2 Section 38.4.26: TIMx register map
®
-M4 with FPU accesses, and not from other bus
Peripheral register map
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