ST STM32L4+ Series Reference Manual page 90

System and memory overview
For STM32L4Rxxx and STM32L4Sxxx devices, the BusMatrix is composed of
•
up to nine masters:
–
•
up to eleven slaves:
–
For STM32L4P5xx and STM32Q5xx devices, the BusMatrix is composed of:
•
nine masters:
–
•
ten slaves:
–
AHB/APB bridges
The two AHB/APB bridges provide full synchronous connections between the AHB and the
two APB buses, allowing flexible selection of the peripheral frequency.
Refer to
address mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and
Flash memory interface). Before using a peripheral you have to enable its clock in the
RCC_AHBxENR and the RCC_APBxENR registers.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
90/2301
CPU AHB system bus, D-Code bus, I-Code bus, DMA1, DMA2, DMA2D,
SDMMC1, LCD-TFT and GFXMMU
FLASH, SRAM1, SRAM2, SRAM3, AHB1 (including APB1 and APB2), AHB2,
GFXMMU, OCTOSTPI1, OCTOSPI2 and FMC
CPU AHB system bus, D-Code bus, I-Code bus, DMA1, DMA2, DMA2D,
SDMMC1, SDMMC2 and LCD-TFT
FLASH, SRAM1, SRAM2, SRAM3, AHB1 (including APB1 and APB2), AHB2,
OCTOSTPI1, OCTOSPI2 and FMC.
Section 2.2.2: Memory map and register boundary addresses on page 92
RM0432 Rev 6
RM0432
for the