ST STM32L4+ Series Reference Manual page 98

Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary
Bus Boundary address
0x4000 9800 - 0x4000 FFFF
0x4000 9400 - 0x4000 97FF
0x4000 8C00 - 0x4000 93FF
0x4000 8400 - 0x4000 87FF
0x4000 8000 - 0x4000 83FF
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
APB1
0x4000 7000 - 0x4000 73FF
0x4000 6800 - 0x4000 6FFF
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00- 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
98/2301
addresses (continued)
Size
Peripheral
(bytes)
26 KB Reserved
1 KB LPTIM2
3 KB Reserved
1 KB I2C4
1 KB LPUART1
1 KB LPTIM1
1 KB OPAMP
1 KB DAC1
1 KB PWR
2 KB Reserved
1 KB CAN1
1 KB CRS
1 KB I2C3
1 KB I2C2
1 KB I2C1
1 KB UART5
1 KB UART4
RM0432 Rev 6
Peripheral register map
-
Section 41.7.11: LPTIM register map
-
Section 49.7.12: I2C register map
Section 51.6.13: LPUART register
map
Section 41.7.11: LPTIM register map
Section 27.5.7: OPAMP register map
Section 22.7.21: DAC register map
Section 5.4.27: PWR register map
and reset value table
-
Section 55.9.5: bxCAN register map
Section 7.7.5: CRS register map
Section 49.7.12: I2C register map
Section 49.7.12: I2C register map
Section 49.7.12: I2C register map
Section 50.7.15: USART register map
Section 50.7.15: USART register map
RM0432