ST STM32L4+ Series Reference Manual page 86

System and memory overview
2 System and memory overview
2.1 System architecture
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
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Up to nine masters:
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Up to eleven slaves:
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The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in
86/2301
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Cortex -M4 with FPU core I-bus
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Cortex -M4 with FPU core D-bus
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Cortex -M4 with FPU core S-bus
DMA1
DMA2
DMA2D (Chrom-Art Accelerator™) memory bus
LCD-TFT controller DMA-bus
SDMMC1 bus
SDMMC2 bus
(only for STM32L4P5xx and STM32L4Q5xx devices)
GFXMMU (Chrom-GRC™) bus
(only for STM32L4Sxxx and STM32L4R5xxx devices)
Internal Flash memory on the I-Code bus
Internal Flash memory on D-Code bus
Internal SRAM1
(192 Kbytes for STM32L4Rxxx and STM32Sxxx devices and
128 Kbytes for STM32L4P5xx and STM32Q5xx devices)
Internal SRAM2 (64 Kbytes)
Internal SRAM3
(384 Kbytes for STM32L4Rxxx and STM32L4Sxxx devices and
128 Kbytes for STM32L4P5xx and STM32L4Q5xx devices)
GFXMMU (Chrom-GRC™)
(only for STM32L4Rxxx and STM32L4Sxxx devices)
AHB1 peripherals including AHB to APB bridges and APB peripherals (connected
to APB1 and APB2)
AHB2 peripherals
Flexible memory controller (FMC)
OCTOSPI1
OCTOSPI2
Figure 1:
RM0432 Rev 6
RM0432