ST STM32L4+ Series Reference Manual page 88

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System and memory overview

Figure 2. System architecture for STM32L4P5xx and STM32L4Q5xx

This bus connects the instruction bus of the Cortex

used by the core to fetch instructions. The target of this bus is a memory containing code

(either internal Flash memory, internal SRAM or external memories through the FMC or

This bus connects the data bus of the Cortex

by the core for literal load and debug access. The target of this bus is a memory containing

code (either internal Flash memory, internal SRAM or external memories through the FMC

or OCTOSPIs).

This bus connects the system bus of the Cortex

used by the core to access data located in a peripheral or SRAM area. The targets of this

bus are the internal SRAM, the AHB1 peripherals including the APB1 and APB2

-M4 core to the BusMatrix. This bus is

-M4 core to the BusMatrix. This bus is used

-M4 core to the BusMatrix. This bus is

RM0432 Rev 6

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