ST STM32L4+ Series Reference Manual page 78

List of figures
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 402. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
Figure 403. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1386
Figure 404. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1387
Figure 405. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387
Figure 406. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
Figure 407. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1389
Figure 408. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389
Figure 409. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 1390
Figure 410. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . 1390
Figure 411. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392
Figure 412. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
Figure 413. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
Figure 414. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396
Figure 415. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
Figure 416. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . 1397
Figure 417. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1398
Figure 418. Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
Figure 419. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
Figure 420. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404
Figure 421. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406
Figure 422. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Figure 423. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409
Figure 424. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410
Figure 425. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
Figure 426. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
Figure 427. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464
Figure 428. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1466
Figure 429. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1466
Figure 430. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467
Figure 431. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
Figure 432. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
Figure 433. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469
Figure 434. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469
Figure 435. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
Figure 436. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1471
Figure 437. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478
Figure 438. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
Figure 439. LPTIM output waveform, single counting mode configuration . . . . . . . . . . . . . . . . . . . . 1483
Figure 440. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
Figure 441. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . 1484
Figure 442. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485
Figure 443. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
Figure 444. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
Figure 445. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
Figure 446. LPTIM output waveform, single counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . . . . . . 1509
Figure 447. LPTIM output waveform, Single counting mode configuration
78/2301 RM0432 Rev 6
RM0432