Table of Contents
Advertisement
3.4
Data interface
ARM DDI0145B
Data transfers take place in the memory stage of the pipeline. The operation of the data
interface is very similar to the instruction interface.
The interface is pipelined with the address and control signals, becoming valid in
phase 2 of the cycle before the transfer. There are four types of data cycle, and these are
indicated by DnMREQ and DSEQ. The timing for these signals is shown in Figure 3-3
on page 3-9. The full encoding for these signals is given in Table 3-3:
For internal cycles, data memory accesses are not required in this instance, the data
interface outputs will retain the state of the previous transfer.
DnRW indicates the direction of the transfer, LOW for reads and HIGH for writes. The
signal becomes valid at approximately the same time as the data address bus.
•
For reads, DDIN[31:0] must be driven with valid data for the falling edge of
GCLK at the end of phase 2.
•
For writes by the processor, data will become valid in phase 1, and remain valid
throughout phase 2.
Both reads and writes are illustrated in Figure 3-3 on page 3-9.
See About the coprocessor interface on page 4-2 for further information on using
DDIN[31:0] and DD[31:0] in unidirectional mode or connecting together to form a
bidirectional bus.
Data transfers may be marked as aborted. The DABORT signal is an input to the
processor with the same timing as the data. Upon completion of the current instruction
in the memory stage of the pipeline, the data abort vector is taken. If the memory control
logic does not make use of the DABORT signal, it must be tied LOW, but with the
exception that data can be transferred to and from the ARM9TDMI core.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM9TDMI Processor Core Memory Interface
Table 3-3 DnMREQ and DSEQ encoding
DnMREQ
DSEQ
Cycle Type
0
0
Non-sequential
0
1
Sequential
1
0
Internal
1
1
Coprocessor Transfer
3-7
Advertisement
Table of Contents
