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Debug Support
5.16
Debug communications channel
5.16.1
Debug comms channel registers
5-48
The ARM9TDMI EmbeddedICE macrocell contains a communication channel for
passing information between the target and the host debugger. This is implemented as
coprocessor 14.
The communications channel consists of a 32-bit wide comms data read register, a
32-bit wide comms data write register and a 6-bit wide comms control register for
synchronized handshaking between the processor and the asynchronous debugger.
These registers are located in fixed locations in the EmbeddedICE register map (as
shown in Figure 5-9 on page 5-40) and are accessed from the processor via MCR and
MRC instructions to coprocessor 14.
The debug comms control register is read only, and allows synchronized handshaking
between the processor and the debugger.
The function of each register bit is described below:
Bits 31:28
Contain a fixed pattern that denotes the EmbeddedICE macrocell version
number, in this case 0010.
Bits 27:2
Unused.
Bit 1
Denotes from the processor's point of view, whether the comms data
write register is free.
If, from the processor's point of view, the comms data write register is
free (W=0), new data may be written.
If it is not free (W=1), the processor must poll until W=0.
If, from the debugger's point of view, W=1, some new data has been
written which may then be scanned out.
Bit 0
Denotes whether there is some new data in the comms data read register.
If, from the processor's point of view, R=1, there is some new data which
may be read via an MRC instruction.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Figure 5-15 Debug comms control register
ARM DDI0145B
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