ST STM32L4+ Series Reference Manual page 7

RM0432
6.4.6
6.4.7
6.4.8
6.4.9
6.4.10
6.4.11
6.4.12
6.4.13
6.4.14
6.4.15
6.4.16
6.4.17
6.4.18
6.4.19
6.4.20
6.4.21
6.4.22
6.4.23
6.4.24
6.4.25
6.4.26
6.4.27
6.4.28
6.4.29
6.4.30
6.4.31
6.4.32
6.4.33
6.4.34
7 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
7.2 CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
PLLSAI2 configuration register (RCC_PLLSAI2CFGR) . . . . . . . . . . . 270
Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 272
Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 274
Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 275
AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . . . . . 277
AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . . . . . 278
AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . 280
APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . . . . . 281
APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . . . . . 283
APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 284
AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . . . . . 286
AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . . . . . 287
AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . . . . . 289
APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 290
APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 292
APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 294
AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Peripherals independent clock configuration register (RCC_CCIPR) . 305
Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 308
Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . . . . . 312
Peripherals independent clock configuration register (RCC_CCIPR2) 313
OCTOSPI delay configuration register (RCC_DLYCFGR) . . . . . . . . . 315
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
RM0432 Rev 6
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