Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1473

Sharc+ processor
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Figure 27-26: Bulk/Low Bandwidth Interrupt Out Transaction
Figure 27-27: Full-Speed/Low Bandwidth Isochronous In Transaction
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Transaction
scheduled
TxPktRdy
set?
Ye s
OUT token sent
DATA0/1 packet sent
STALL
received?
No
ACK
received?
Ye s
NAK limit
NA K
No
reached?
received?
Error coun t
Yes
cleared
Error count
incremented
NAK timeout set
Endpoint halted
Interrupt generated
No
Error count
= 3?
Host actions are shown white. USB actions are shaded
Host actions are shown white. USB actions are shaded
No
Ta rget has
RxStall set
shut down pipe
Yes
TxPktRdy cleared
Error count cleared
Interrupt generated
TxPktRdy cleared
Yes
Error count cleared
Interrupt generated
No
Transaction
complete
No
Implies problem at
periphe ral end of
Error bit set
connection.
Yes
TxPktRdy cleared
Error count cleared
Interrupt generated
Transaction
scheduled
No
ReqPkt set?
Yes
IN token sent
No
Data0
received?
Yes
ReqPkt cleared
RxPktRdy set
Interrupt generated
Transaction
complete
USB Programming Model
Transaction
deemed
completed
27–61

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