Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1470

USB Programming Model
Host Mode Flow Charts
Figure 27-20: USB Control SETUP Phase
Figure 27-21: Control In Data Phase
27–58
Transaction
scheduled
TxPktRdy
and SetupPkt
both set?
Yes
SETUP token sent
DATA 0 packet sent
STALL
received?
No
ACK
received?
No
Yes
No
NAK limit NAK
reached? received?
Error count
No
Yes
cleared
Error count
incremented
NAK timeout set
Endpoint halted
Interrupt generated
No
Error count
= 3?
For each IN
packet reque sted
in SETUP pha se
ReqPkt set?
Ye s
IN token sent
STALL
received?
No
Ye s
No
NAK limit NAK
reached ? received?
No
Error coun t
Yes
cleared
NAK timeou t set DATA0/1
Endpo int halted
received?
Interrupt gene rated
No
Error coun t
incremented
No Ye s
Error coun t
= 3?
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Host actions are shown white. USB actions are shaded
No
Command not
RxStall set
supported by target
Yes
TxPktRdy cleared
Error count cleared
Interrupt generated
TxPktRdy cleared
Yes
Error count cleared
Interrupt generated
Transaction
complete
Implies problem at
peripheral end of
Error bit set
Yes
connection.
TxPktRdy cleared
Error count cleared
Interrupt generated
Host actions are shown white. USB actions are shaded
No
RxStall set
Problem in data sent
Ye s
ReqPkt cleared
Error coun t cleared
Interrupt gene rated
ReqP kt cleared
Ye s
ACK sent
Error coun t cleared
RxPktRdy set
Interrupt gene rated
Transaction
complete
Implies problem at
Error bit set periphe ral end of
ReqPkt cleared conne ction.
Error coun t cleared
Interrupt gene rated
Transaction dee med
Transaction
deemed
completed
completed