12.8.10 Conflict Between Overflow/Underflow And Counter Clearing; Figure 12.52 Conflict Between Overflow And Counter Clearing - Renesas H8S Series Hardware Manual

12.8.10 Conflict between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence. Figure 12.52 shows the operation timing when a
TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.

Figure 12.52 Conflict between Overflow and Counter Clearing

φ
TCNT input
clock
TCNT H'FFFF
Counter
clear signal
TGF
Disabled
TCFV
Section 12 16-Bit Timer Pulse Unit (TPU)
H'0000
Rev. 3.00 Jul. 14, 2005 Page 375 of 986
REJ09B0098-0300