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Renesas H8SX/1650 Manuals
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Renesas H8SX/1650 manual available for free PDF download: Hardware Manual
Renesas H8SX/1650 Hardware Manual (692 pages)
Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
Brand:
Renesas
| Category:
Computer Hardware
| Size: 4.61 MB
Table of Contents
How to Use this Manual
5
Table of Contents
9
Section 1 Overview
23
Features
23
Applications
23
Overview of Functions
24
List of Products
29
Block Diagram
30
Pin Assignments
31
Pin Functions
32
Section 2 CPU
37
Features
37
CPU Operating Modes
39
Normal Mode
39
Middle Mode
41
Advanced Mode
42
Maximum Mode
43
Instruction Fetch
45
Address Space
45
Registers
46
General Registers
47
Program Counter (PC)
48
Condition-Code Register (CCR)
48
Extended Control Register (EXR)
50
Vector Base Register (VBR)
50
Short Address Base Register (SBR)
50
Multiply-Accumulate Register (MAC)
51
Initial Register Values
51
Data Formats
52
General Register Data Formats
52
Memory Data Formats
53
Instruction Set
54
Instructions and Addressing Modes
56
Table of Instructions Classified by Function
60
Basic Instruction Formats
71
Addressing Modes and Effective Address Calculation
72
Register Direct-Rn
73
Register Indirect-@Ern
73
Register Indirect with Displacement-@(D:2, Ern), @(D:16, Ern), or @(D:32, Ern)
73
Index Register Indirect with Displacement-@(D:16,Rnl.b), @(D:32,Rnl.b), @(D:16,Rn.w), @(D:32,Rn.w), @(D:16,Ern.l), or @(D:32,Ern.l)
73
Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement-@Ern+, @−Ern, @+Ern, or @Ern
74
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
75
Immediate-#XX:8, #XX:16, or #XX:32
76
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
77
Program-Counter Relative with Index Register-@(Rnl.b, PC), @(Rn.w, PC), or @(Ern.l, PC)
77
Memory Indirect-@@Aa:8
77
Extended Memory Indirect-@@Vec:7
78
Effective Address Calculation
78
MOVA Instruction
80
Processing States
81
Section 3 MCU Operating Modes
83
Operating Mode Selection
83
Register Descriptions
84
Mode Control Register (MDCR)
84
System Control Register (SYSCR)
86
Operating Mode Descriptions
88
Mode 4
88
Mode 5
88
Pin Functions
89
Address Map
90
Address Map (Advanced Mode)
90
Section 4 Exception Handling
91
Exception Handling Types and Priority
91
Exception Sources and Exception Handling Vector Table
92
Reset
94
Reset Exception Handling
94
Interrupts after Reset
95
On-Chip Peripheral Functions after Reset Release
95
Traces Exception Handling
97
Address Error
98
Address Error Source
98
Address Error Exception Handling
99
Interrupts
100
Interrupt Sources
100
Interrupt Exception Handling
100
Instruction Exception Handling
101
Trap Instruction Exception Handling
101
Sleep Instruction Exception Handling
102
Exception Handling by Illegal Instruction
103
Stack Status after Exception Handling
104
Usage Note
105
Section 5 Interrupt Controller
107
Features
107
Input/Output Pins
109
Register Descriptions
109
Interrupt Control Register (INTCR)
110
CPU Priority Control Register (CPUPCR)
111
Interrupt Priority Registers a to C, E to H, K, and L (IPRA to IPRC, IPRE to IPRH, IPRK, and IPRL)
112
IRQ Enable Register (IER)
114
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
116
IRQ Status Register (ISR)
120
Software Standby Release IRQ Enable Register (SSIER)
121
Interrupt Sources
122
External Interrupts
122
Internal Interrupts
123
Interrupt Exception Handling Vector Table
124
Interrupt Control Modes and Interrupt Operation
128
Interrupt Control Mode 0
128
Interrupt Control Mode 2
130
Interrupt Exception Handling Sequence
132
Interrupt Response Times
133
DTC Activation by Interrupt
134
CPU Priority Control Function over DTC
137
Usage Notes
139
Conflict between Interrupt Generation and Disabling
139
Instructions that Disable Interrupts
140
Times When Interrupts Are Disabled
140
Interrupts During Execution of EEPMOV Instruction
140
Interrupts During Execution of MOVMD and MOVSD Instructions
140
Interrupts Source Flag of Peripheral Modules
141
Section 6 Bus Controller (BSC)
143
Features
143
Register Descriptions
146
Bus Width Control Register (ABWCR)
146
Access State Control Register (ASTCR)
148
Wait Control Registers a and B (WTCRA, WTCRB)
149
Read Strobe Timing Control Register (RDNCR)
154
CS Assertion Period Control Registers (CSACR)
155
Idle Control Register (IDLCR)
157
Bus Control Register 1 (BCR1)
159
Bus Control Register 2 (BCR2)
161
Endian Control Register (ENDIANCR)
162
SRAM Mode Control Register (SRAMCR)
163
Burst ROM Interface Control Register (BROMCR)
164
Address/Data Multiplexed I/O Control Register (MPXCR)
166
Bus Configuration
167
Multi-Clock Function and Number of Access Cycles
168
External Bus
172
Input/Output Pins
172
Area Division
175
Chip Select Signals
176
External Bus Interface
177
Area and External Bus Interface
181
Endian and Data Alignment
185
Basic Bus Interface
189
Data Bus
189
I/O Pins Used for Basic Bus Interface
189
Basic Timing
190
Wait Control
196
Read Strobe (RD) Timing
198
Extension of Chip Select (CS) Assertion Period
199
Byte Control SRAM Interface
201
Byte Control SRAM Space Setting
201
Data Bus
201
I/O Pins Used for Byte Control SRAM Interface
202
Basic Timing
203
Wait Control
205
Read Strobe (RD)
207
Extension of Chip Select (CS) Assertion Period
207
Burst ROM Interface
207
Burst ROM Space Setting
207
Data Bus
208
I/O Pins Used for Burst ROM Interface
208
Basic Timing
209
Wait Control
211
Read Strobe (RD) Timing
211
Extension of Chip Select (CS) Assertion Period
211
Address/Data Multiplexed I/O Interface
211
Address/Data Multiplexed I/O Space Setting
211
Address/Data Multiplex
212
Data Bus
212
I/O Pins Used for Address/Data Multiplexed I/O Interface
213
Basic Timing
214
Address Cycle Control
216
Wait Control
217
Read Strobe (RD) Timing
217
Extension of Chip Select (CS) Assertion Period
218
Idle Cycle
220
Operation
220
Pin States in Idle Cycle
228
Bus Release
229
Operation
229
Pin States in External Bus Released State
230
Transition Timing
231
Internal Bus
232
Access to Internal Address Space
232
Write Data Buffer Function
233
Write Data Buffer Function for External Data Bus
233
Write Data Buffer Function for Peripheral Modules
234
Bus Arbitration
235
Operation
235
Bus Transfer Timing
236
Bus Controller Operation in Reset
237
Usage Notes
237
Section 7 Data Transfer Controller (DTC)
239
Features
239
Register Descriptions
241
DTC Mode Register a (MRA)
242
DTC Mode Register B (MRB)
243
DTC Source Address Register (SAR)
245
DTC Destination Address Register (DAR)
245
DTC Transfer Count Register a (CRA)
246
DTC Transfer Count Register B (CRB)
246
DTC Enable Registers a to H (DTCERA to DTCERH)
247
DTC Control Register (DTCCR)
248
DTC Vector Base Register (DTCVBR)
249
Activation Sources
249
Location of Transfer Information and DTC Vector Table
250
Operation
253
Bus Cycle Division
255
Transfer Information Read Skip Function
257
Transfer Information Writeback Skip Function
258
Normal Transfer Mode
258
Repeat Transfer Mode
259
Block Transfer Mode
261
Chain Transfer
262
Operation Timing
263
Number of DTC Execution Cycles
265
DTC Bus Release Timing
266
DTC Priority Level Control to the CPU
266
DTC Activation by Interrupt
267
Examples of Use of the DTC
268
Normal Transfer Mode
268
Chain Transfer
269
Chain Transfer When Counter = 0
270
Interrupt Sources
271
Usage Notes
271
Module Stop State Setting
271
On-Chip RAM
272
DTCE Bit Setting
272
Chain Transfer
272
Transfer Information Start Address, Source Address, and Destination Address
272
Endian
272
Section 8 I/O Ports
273
Register Descriptions
279
Data Direction Register (Pnddr) (N = 1 to 3, 6, A, B, D to F, H, and I)
280
Data Register (Pndr) (N = 1 to 3, 6, A, B, D to F, H, and I)
281
Port Register (Portn) (N = 1 to 3, 5, 6, A, B, D to F, H, and I)
281
Input Buffer Control Register (Pnicr) (N = 1 to 3, 5, 6, A, B, D to F, H, and I)
282
Pull-Up MOS Control Register (Pnpcr) (N = D to F, H, and I)
283
Open-Drain Control Register (Pnodr) (N = 2 and F)
284
Output Buffer Control
284
Port 1
284
Port 2
287
Port 3
291
Port 5
295
Port 6
296
Port a
298
Port B
302
Port D
304
Port E
304
Port F
305
Port H
308
Port I
308
Port Function Controller
314
Port Function Control Register 0 (PFCR0)
314
Port Function Control Register 1 (PFCR1)
315
Port Function Control Register 2 (PFCR2)
316
Port Function Control Register 4 (PFCR4)
318
Port Function Control Register 6 (PFCR6)
319
Port Function Control Register 9 (PFCR9)
320
Port Function Control Register B (PFCRB)
322
Port Function Control Register C (PFCRC)
323
Usage Notes
325
Notes on Input Buffer Control Register (ICR) Setting
325
Notes on Port Function Control Register (PFCR) Settings
325
Section 9 16-Bit Timer Pulse Unit (TPU)
327
Features
327
Input/Output Pins
331
Register Descriptions
332
Timer Control Register (TCR)
334
Timer Mode Register (TMDR)
340
Timer I/O Control Register (TIOR)
341
Timer Interrupt Enable Register (TIER)
359
Timer Status Register (TSR)
361
Timer Counter (TCNT)
365
Timer General Register (TGR)
365
Timer Start Register (TSTR)
366
Timer Synchronous Register (TSYR)
367
Operation
368
Basic Functions
368
Synchronous Operation
374
Buffer Operation
376
Cascaded Operation
379
PWM Modes
381
Phase Counting Mode
386
Interrupt Sources
392
DTC Activation
394
A/D Converter Activation
394
Operation Timing
395
Input/Output Timing
395
Interrupt Signal Timing
399
Usage Notes
403
Module Stop State Setting
403
Input Clock Restrictions
403
Caution on Cycle Setting
404
Conflict between TCNT Write and Clear Operations
404
Conflict between TCNT Write and Increment Operations
405
Conflict between TGR Write and Compare Match
405
Conflict between Buffer Register Write and Compare Match
406
Conflict between TGR Read and Input Capture
406
Conflict between TGR Write and Input Capture
407
Conflict between Buffer Register Write and Input Capture
408
Conflict between Overflow/Underflow and Counter Clearing
409
Conflict between TCNT Write and Overflow/Underflow
409
Multiplexing of I/O Pins
410
Interrupts and Module Stop State
410
Section 10 Programmable Pulse Generator (PPG)
411
Features
411
Input/Output Pins
413
Register Descriptions
414
Next Data Enable Registers H, L (NDERH, NDERL)
414
Output Data Registers H, L (PODRH, PODRL)
416
Next Data Registers H, L (NDRH, NDRL)
417
PPG Output Control Register (PCR)
420
PPG Output Mode Register (PMR)
421
Operation
423
Output Timing
423
Sample Setup Procedure for Normal Pulse Output
424
Example of Normal Pulse Output (Example of 5-Phase Pulse Output)
425
Non-Overlapping Pulse Output
426
Sample Setup Procedure for Non-Overlapping Pulse Output
428
Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output)
429
Inverted Pulse Output
431
Pulse Output Triggered by Input Capture
432
Usage Notes
432
Module Stop State Setting
432
Operation of Pulse Output Pins
432
Section 11 8-Bit Timers (TMR)
433
Features
433
Input/Output Pins
436
Register Descriptions
437
Timer Counter (TCNT)
438
Time Constant Register a (TCORA)
438
Time Constant Register B (TCORB)
439
Timer Control Register (TCR)
439
Timer Counter Control Register (TCCR)
441
Timer Control/Status Register (TCSR)
443
Operation
447
Pulse Output
447
Reset Input
448
Operation Timing
449
TCNT Count Timing
449
Timing of CMFA and CMFB Setting at Compare Match
449
Timing of Timer Output at Compare Match
450
Timing of Counter Clear by Compare Match
450
Timing of TCNT External Reset
451
Timing of Overflow Flag (OVF) Setting
451
Operation with Cascaded Connection
452
16-Bit Counter Mode
452
Compare Match Count Mode
452
Interrupt Sources
453
Interrupt Sources and DTC Activation
453
A/D Converter Activation
453
Usage Notes
454
Notes on Setting Cycle
454
Conflict between TCNT Write and Clear
454
Conflict between TCNT Write and Increment
455
Conflict between TCOR Write and Compare Match
455
Conflict between Compare Matches a and B
456
Switching of Internal Clocks and TCNT Operation
456
Mode Setting with Cascaded Connection
458
Module Stop State Setting
458
Interrupts in Module Stop State
458
Section 12 Watchdog Timer (WDT)
459
Features
459
Input/Output Pin
460
Register Descriptions
460
Timer Counter (TCNT)
460
Timer Control/Status Register (TCSR)
461
Reset Control/Status Register (RSTCSR)
463
Operation
464
Watchdog Timer Mode
464
Interval Timer Mode
466
Interrupt Source
466
Usage Notes
467
Notes on Register Access
467
Conflict between Timer Counter (TCNT) Write and Increment
468
Changing Values of Bits CKS2 to CKS0
468
Switching between Watchdog Timer Mode and Interval Timer Mode
468
Internal Reset in Watchdog Timer Mode
469
System Reset by WDTOVF Signal
469
Transition to Watchdog Timer Mode or Software Standby Mode
469
Section 13 Serial Communication Interface (SCI)
471
Features
471
Input/Output Pins
473
Register Descriptions
474
Receive Shift Register (RSR)
476
Receive Data Register (RDR)
476
Transmit Data Register (TDR)
476
Transmit Shift Register (TSR)
477
Serial Mode Register (SMR)
477
Serial Control Register (SCR)
480
Serial Status Register (SSR)
485
Smart Card Mode Register (SCMR)
492
Bit Rate Register (BRR)
493
Serial Extended Mode Register (SEMR)
501
Operation in Asynchronous Mode
503
Data Transfer Format
504
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
505
Clock
506
SCI Initialization (Asynchronous Mode)
507
Serial Data Transmission (Asynchronous Mode)
508
Serial Data Reception (Asynchronous Mode)
510
Multiprocessor Communication Function
514
Multiprocessor Serial Data Transmission
516
Multiprocessor Serial Data Reception
517
Operation in Clocked Synchronous Mode
520
Clock
520
SCI Initialization (Clocked Synchronous Mode)
521
Serial Data Transmission (Clocked Synchronous Mode)
522
Serial Data Reception (Clocked Synchronous Mode)
524
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
526
Operation in Smart Card Interface Mode
528
Sample Connection
528
Data Format (Except in Block Transfer Mode)
529
Block Transfer Mode
530
Receive Data Sampling Timing and Reception Margin
531
Initialization
532
Data Transmission (Except in Block Transfer Mode)
533
Serial Data Reception (Except in Block Transfer Mode)
536
Clock Output Control
537
Interrupt Sources
539
Interrupts in Normal Serial Communication Interface Mode
539
Interrupts in Smart Card Interface Mode
540
Usage Notes
541
Module Stop State Setting
541
Break Detection and Processing
541
Mark State and Break Detection
541
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
541
Relation between Writing to TDR and TDRE Flag
542
Restrictions on Using DTC
542
SCI Operations During Power-Down State
543
Section 14 A/D Converter
547
Features
547
Input/Output Pins
549
Register Descriptions
549
A/D Data Registers a to H (ADDRA to ADDRH)
550
A/D Control/Status Register (ADCSR)
551
A/D Control Register (ADCR)
553
Operation
554
Single Mode
554
Scan Mode
555
Input Sampling and A/D Conversion Time
557
External Trigger Input Timing
559
Interrupt Source
559
A/D Conversion Accuracy Definitions
560
Usage Notes
562
Module Stop State Setting
562
Permissible Signal Source Impedance
562
Influences on Absolute Accuracy
563
Setting Range of Analog Power Supply and Other Pins
563
Notes on Board Design
563
Notes on Noise Countermeasures
564
A/D Input Hold Function in Software Standby Mode
565
Section 15 D/A Converter
567
Features
567
Input/Output Pins
568
Register Descriptions
568
D/A Data Registers 0 and 1 (DADR0 and DADR1)
568
D/A Control Register 01 (DACR01)
569
Operation
571
Usage Notes
572
Module Stop State Setting
572
D/A Output Hold Function in Software Standby Mode
572
Section 16 RAM
573
Section 17 Clock Pulse Generator
575
Register Description
576
System Clock Control Register (SCKCR)
576
Oscillator
579
Connecting Crystal Resonator
579
External Clock Input
580
PLL Circuit
580
Frequency Divider
580
Usage Notes
581
Notes on Clock Pulse Generator
581
Notes on Resonator
582
Notes on Board Design
582
Section 18 Power-Down States
585
Features
585
Register Descriptions
587
Standby Control Register (SBYCR)
588
Module Stop Control Registers a and B (MSTPCRA and MSTPCRB)
591
Module Stop Control Register C (MSTPCRC)
594
Multi-Clock Function
595
Module Stop Function
595
Sleep Mode
596
Transition to Sleep Mode
596
Clearing Sleep Mode
596
All-Module-Clock-Stop Mode
597
Software Standby Mode
597
Transition to Software Standby Mode
597
Clearing Software Standby Mode
598
Setting Oscillation Settling Time after Clearing Software Standby Mode
598
Software Standby Mode Application Example
601
Hardware Standby Mode
602
Transition to Hardware Standby Mode
602
Clearing Hardware Standby Mode
602
Hardware Standby Mode Timing
602
Timing Sequence at Power-On
603
Sleep Instruction Exception Handling
604
Bφ Clock Output Control
607
Usage Notes
608
I/O Port Status
608
18.11.2 Current Consumption During Oscillation Settling Standby Period
608
18.11.3 DTC Module Stop
608
18.11.4 On-Chip Peripheral Module Interrupts
608
18.11.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC
608
Section 19 List of Registers
609
Register Addresses (Address Order)
610
Register Bits
619
Register States in each Operating Mode
629
Section 20 Electrical Characteristics
639
Absolute Maximum Ratings
639
DC Characteristics
640
AC Characteristics
643
Clock Timing
644
Control Signal Timing
646
Bus Timing
647
Timing of On-Chip Peripheral Modules
662
A/D Conversion Characteristics
666
D/A Conversion Characteristics
667
Appendix
669
Port States in each Pin State
669
Product Lineup
672
Package Dimensions
673
Treatment of Unused Pins
674
Main Revisions and Additions in this Edition
677
Index
683
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