Notes; Usage Notes - Renesas H8S Series Hardware Manual

Section 22 Boundary Scan (JTAG)
(6) IDCODE
Instruction code: B'1110
When the IDCODE instruction is enabled, the value of the ID code register is output from the
ETDO pin with LSB first when the TAP controller is in the Shift-DR state. While the IDCODE
instruction is being executed, the test circuit does not affect the system circuit.
When the TAP controller is in the Test-Logic-Reset state, the instruction register is initialized to
the IDCODE instruction.
22.5.2

Notes

1. Boundary scan mode does not cover power-supply-related pins (VCC, VCL, VSS, AVCC,
AVSS, and AVref).
2. Boundary scan mode covers clock-related pins (EXTAL, XTAL, X1, and X2).
3. Boundary scan mode does not cover reset- and standby-related pins (RES, STBY, and RESO).
4. Boundary scan mode does not cover JTAG-related pins (ETCK, ETDI, ETDO, ETMS, and
ETRST).
5. Fix the MD2 pin low.
22.6

Usage Notes

1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not
the JTAG is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For
details, see section 26, Electrical Characteristics. To activate the JTAG after a reset, drive the
ETRST pin to 1 and specify the ETCK, ETMS, and ETDI pins to any value. If the JTAG is not
to be activated, drive the ETRST, ETCK, ETMS, and ETDI pins to 1 or the high-impedance
state. These pins are internally pulled up and are noted in standby mode.
2. The following must be considered when the power-on reset signal is applied to the ETRST
pin.
 The reset signal must be applied at power-on.
 To prevent the LSI system operation from being affected by the ETRST pin of the board
tester, circuits must be separated.
 Alternatively, to prevent the ETRST pin of the board tester from being affected by the LSI
system reset, circuits must be separated.
Figure 22.3 shows a design example of the reset signal circuit wherein no reset signal
interference occurs.
Rev. 3.00 Jul. 14, 2005 Page 846 of 986
REJ09B0098-0300