Renesas R4F2114R Manuals

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Renesas R4F2114R Hardware Manual (1038 pages)

16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 5.77 MB

General Precautions on Handling of Product
4
Preface
6
Table of Contents
11
Section 1 Overview

49
Section 2 CPU

67
Section 3 MCU Operating Modes

107
- Operating Mode Selection
  107
- Register Descriptions
  108
- Operating Mode Descriptions
  115
  - Mode 2
    115
  - Mode 3
    115
- Address Map
  115
- Figure 3.1 Address Map
  116
Section 4 Exception Handling

117
Section 5 Interrupt Controller

127
Section 6 Bus Controller (BSC)

177
- Features
  177
- Figure 6.1 Block Diagram of BSC
  177
- Register Descriptions
  178
  - Bus Control Register (BCR)
    178
  - Wait State Control Register (WSCR)
    179
- Bus Arbitration
  180
  - Priority of Bus Masters
    180
  - Bus Transfer Timing
    180
Section 7 Data Transfer Controller (DTC)

183
Section 8 I/O Ports

207
- Table 8.1 Port Functions
  207
- Port 1
  212
  - Port 1 Data Direction Register (P1DDR)
    212
  - Port 1 Data Register (P1DR)
    213
  - Port 1 Pull-Up MOS Control Register (P1PCR)
    213
  - Pin Functions
    214
  - Port 1 Input Pull-Up MOS
    214
  - Table 8.2 Port 1 Input Pull-Up MOS States
    214
- Port 2
  215
  - Port 2 Data Direction Register (P2DDR)
    215
  - Port 2 Data Register (P2DR)
    216
  - Port 2 Pull-Up MOS Control Register (P2PCR)
    216
  - Pin Functions
    217
  - Port 2 Input Pull-Up MOS
    218
  - Table 8.3 Port 2 Input Pull-Up MOS States
    218
- Port 3
  219
  - Port 3 Data Direction Register (P3DDR)
    219
  - Port 3 Data Register (P3DR)
    220
  - Port 3 Pull-Up MOS Control Register (P3PCR)
    220
  - Pin Functions
    221
  - Port 3 Input Pull-Up MOS
    221
  - Table 8.4 Port 3 Input Pull-Up MOS States
    221
- Port 4
  222
  - Port 4 Data Direction Register (P4DDR)
    222
  - Port 4 Data Register (P4DR)
    223
  - Pin Functions
    223
- Port 5
  226
  - Port 5 Data Direction Register (P5DDR)
    226
  - Port 5 Data Register (P5DR)
    226
  - Pin Functions
    227
- Port 6
  228
- Port 7
  237
  - Port 7 Input Data Register (P7PIN)
    237
  - Pin Functions
    238
- Port 8
  239
  - Port 8 Data Direction Register (P8DDR)
    239
  - Port 8 Data Register (P8DR)
    240
  - Pin Functions
    241
- Port 9
  244
  - Port 9 Data Direction Register (P9DDR)
    244
  - Port 9 Data Register (P9DR)
    245
  - Port 9 Pull-Up MOS Control Register (P9PCR)
    245
  - Pin Functions
    246
  - Port 9 Input Pull-Up MOS
    248
  - Table 8.6 Port 9 Input Pull-Up MOS States
    248
- Port a
  249
  - Port a Data Direction Register (PADDR)
    249
  - Port a Output Data Register (PAODR)
    250
  - Port a Input Data Register (PAPIN)
    250
  - Pin Functions
    251
- Port B
  252
  - Port B Data Direction Register (PBDDR)
    252
  - Port B Output Data Register (PBODR)
    253
  - Port B Input Data Register (PBPIN)
    253
  - Pin Functions
    254
  - Port B Input Pull-Up MOS
    256
  - Table 8.7 Port B Input Pull-Up MOS States
    256
- Port C
  257
- Port D
  265
  - Port D Data Direction Register (PDDDR)
    265
  - Port D Output Data Register (PDODR)
    266
  - Port D Input Data Register (PDPIN)
    266
  - Pin Functions
    267
  - Port D Nch-OD Control Register (PDNOCR)
    271
  - Pin Functions
    271
  - Port D Input Pull-Up MOS
    272
  - Table 8.9 Port D Input Pull-Up MOS States
    272
- Port E
  273
- Port F
  275
  - Port F Data Direction Register (PFDDR)
    275
  - Port F Output Data Register (PFODR)
    276
  - Port F Input Data Register (PFPIN)
    276
  - Pin Functions
    277
  - Port F Nch-OD Control Register (PFNOCR)
    279
  - Pin Functions
    279
  - Port F Input Pull-Up MOS
    280
  - Table 8.11 Port F Input Pull-Up MOS States
    280
- Port G
  281
  - Port G Data Direction Register
    281
  - Port G Output Data Register
    282
  - Port G Input Data Register
    282
  - Noise Canceller Enable Register
    283
  - Noise Canceller Mode Control Register
    283
  - Noise Cancel Cycle Setting Register
    284
  - Pin Functions
    285
  - Port G Nch-OD Control Register
    290
  - Pin Functions
    290
- Change of Peripheral Function Pins
  291
Section 9 8-Bit PWM Timer (PWM)

295
Section 10 14-Bit PWM Timer (PWMX)

307
Section 11 16-Bit Free-Running Timer (FRT)

325
Section 12 16-Bit Timer Pulse Unit (TPU)

353
Section 13 8-Bit Timer (TMR)

425
Section 14 Watchdog Timer (WDT)

461
- Features
  461
- Figure 14.1 Block Diagram of WDT
  462
- Input/Output Pins
  463
- Register Descriptions
  463
  - Timer Counter (TCNT)
    463
  - Table 14.1 Pin Configuration
    463
  - Timer Control/Status Register (TCSR)
    464
- Operation
  468
- Interrupt Sources
  471
- Table 14.2 WDT Interrupt Source
  471
- Usage Notes
  472
Section 15 Serial Communication Interface (SCI, Irda)

475
Section 16 I C Bus Interface (IIC)

553
Section 17 Keyboard Buffer Control Unit (KBU)

629
Section 18 LPC Interface (LPC)

661
Section 19 A/D Converter

765
- Features
  765
- Figure 19.1 Block Diagram of A/D Converter
  766
- Input/Output Pins
  767
- Table 19.1 Pin Configuration
  767
- Register Descriptions
  768
- Operation
  771
  - Single Mode
    771
  - Scan Mode
    771
  - Input Sampling and A/D Conversion Time
    772
  - Figure 19.2 A/D Conversion Timing
    773
  - External Trigger Input Timing
    774
  - Figure 19.3 External Trigger Input Timing
    774
  - Table 19.3 A/D Conversion Time (Single Mode)
    774
- Interrupt Source
  775
- A/D Conversion Accuracy Definitions
  775
- Table 19.4 A/D Converter Interrupt Source
  775
- Figure 19.4 A/D Conversion Accuracy Definitions
  776
- Figure 19.5 A/D Conversion Accuracy Definitions
  776
- Usage Notes
  777
Section 20 RAM

781
Section 21 Flash Memory (0.18-ΜM F-ZTAT Version)

783
Section 22 Boundary Scan (JTAG)

875
- Features
  875
- Figure 22.1 JTAG Block Diagram
  876
- Input/Output Pins
  877
- Table 22.1 Pin Configuration
  877
- Register Descriptions
  878
- Operation
  890
  - TAP Controller State Transitions
    890
  - JTAG Reset
    891
  - Figure 22.2 TAP Controller State Transitions
    891
- Boundary Scan
  892
  - Supported Instructions
    892
  - Notes
    894
- Usage Notes
  894
- Figure 22.3 Reset Signal Circuit Without Reset Signal Interference
  895
- Figure 22.4 Serial Data Input/Output (1)
  896
- Figure 22.5 Serial Data Input/Output (2)
  896
Section 23 Clock Pulse Generator

897
Section 24 Power-Down Modes

907
- Register Descriptions
  908
- Mode Transitions and LSI States
  914
- Figure 24.1 Mode Transition Diagram
  915
- Table 24.2 LSI Internal States in each Operating Mode
  916
- Medium-Speed Mode
  918
- Sleep Mode
  919
- Figure 24.2 Medium-Speed Mode Timing
  919
- Software Standby Mode
  920
- Figure 24.3 Software Standby Mode Application Example
  921
- Hardware Standby Mode
  922
- Figure 24.4 Hardware Standby Mode Timing
  922
- Watch Mode
  923
- Subsleep Mode
  924
- Subactive Mode
  925
- Module Stop Mode
  926
- Direct Transitions
  926
- Usage Notes
  927
Section 25 List of Registers

929
Section 26 Electrical Characteristics

995
- Absolute Maximum Ratings
  995
- Table 26.1 Absolute Maximum Ratings
  995
- DC Characteristics
  996
- Table 26.2 DC Characteristics (1)
  996
- Table 26.2 DC Characteristics (2)
  998
- Table 26.2 DC Characteristics (3) Using LPC Function
  999
- Table 26.3 Permissible Output Currents
  1000
- Table 26.4 Bus Drive Characteristics
  1001
- Figure 26.1 Darlington Transistor Drive Circuit (Example)
  1002
- Figure 26.2 LED Drive Circuit (Example)
  1002
- AC Characteristics
  1003
  - Figure 26.3 Output Load Circuit
    1003
  - Clock Timing
    1004
  - Figure 26.4 System Clock Timing
    1004
  - Table 26.5 Clock Timing
    1004
  - Figure 26.5 Oscillation Stabilization Timing
    1005
  - Figure 26.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)
    1005
  - Control Signal Timing
    1006
  - Figure 26.7 Reset Input Timing
    1006
  - Table 26.6 Control Signal Timing
    1006
  - Figure 26.8 Interrupt Input Timing
    1007
  - Timing of On-Chip Peripheral Modules
    1007
  - Table 26.7 Timing of On-Chip Peripheral Modules
    1008
  - Figure 26.10 FRT Input/Output Timing
    1009
  - Figure 26.11 FRT Clock Input Timing
    1009
  - Figure 26.9 I/O Port Input/Output Timing
    1009
  - Figure 26.12 TPU Input/Output Timing
    1010
  - Figure 26.13 TPU Clock Input Timing
    1010
  - Figure 26.14 8-Bit Timer Output Timing
    1010
  - Figure 26.15 8-Bit Timer Clock Input Timing
    1010
  - Figure 26.16 8-Bit Timer Reset Input Timing
    1011
  - Figure 26.17 PWM, PWMX Output Timing
    1011
  - Figure 26.18 SCK Clock Input Timing
    1011
  - Figure 26.19 SCI Input/Output Timing (Clock Synchronous Mode)
    1011
  - Figure 26.20 A/D Converter External Trigger Input Timing
    1012
  - Figure 26.21 WDT Output Timing (RESO)
    1012
  - Table 26.8 KBU Bus Timing
    1012
  - Figure 26.22 Keyboard Buffer Control Unit Timing
    1013
  - Table 26.9 I 2 C Bus Timing
    1014
  - Figure 26.23 I C Bus Interface Input/Output Timing
    1015
  - Table 26.10 LPC Timing
    1015
  - Figure 26.24 LPC Interface Timing
    1016
  - Figure 26.25 Test Conditions for Tester
    1016
  - Figure 26.26 JTAG ETCK Timing
    1017
  - Table 26.11 JTAG Timing
    1017
  - Figure 26.27 Reset Hold Timing
    1018
  - Figure 26.28 JTAG Input/Output Timing
    1018
  - A/D Conversion Characteristics
    1019
  - Table 26.12 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion)
    1019
- Flash Memory Characteristics
  1020
- Table 26.13 Flash Memory Characteristics
  1020
- Usage Notes
  1021
- Figure 26.29 Connection of VCL Capacitor
  1021
Appendix

1023
- I/O Port States in each Pin State
  1023
  - Table A.1 I/O Port States in each Pin State
    1023
- Product Lineup
  1024
- Package Dimensions
  1025
- Figure C.1 Package Dimensions (TFP-144)
  1025
Index

1027

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Renesas R4F2114R Manuals

Renesas R4F2114R Hardware Manual (1038 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller (BSC)

Section 7 Data Transfer Controller (DTC)

Section 8 I/O Ports

Section 9 8-Bit PWM Timer (PWM)

Section 10 14-Bit PWM Timer (PWMX)

Section 11 16-Bit Free-Running Timer (FRT)

Section 12 16-Bit Timer Pulse Unit (TPU)

Section 13 8-Bit Timer (TMR)

Section 14 Watchdog Timer (WDT)

Section 15 Serial Communication Interface (SCI, Irda)

Section 16 I C Bus Interface (IIC)

Section 17 Keyboard Buffer Control Unit (KBU)

Section 18 LPC Interface (LPC)

Section 19 A/D Converter

Section 20 RAM

Section 21 Flash Memory (0.18-ΜM F-ZTAT Version)

Section 22 Boundary Scan (JTAG)

Section 23 Clock Pulse Generator

Section 24 Power-Down Modes

Section 25 List of Registers

Section 26 Electrical Characteristics

Appendix

Index

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