Section 21 Flash Memory (0.18-Μm F-Ztat Version); Features - Renesas H8S Series Hardware Manual

Section 21 Flash Memory (0.18-µm F-ZTAT Version)
The flash memory has the following features. Figure 21.1 shows a block diagram of the flash
memory.
21.1

Features

• Size
Product Classification
H8S/2114R
• Two flash-memory MATs according to LSI initiation mode
The on-chip flash memory has two memory spaces in the same address space (hereafter
referred to as memory MATs). The mode setting at initiation determines which memory MAT
is initiated first. The MAT can be switched by using the bank-switching method after
initiation.
 The user MAT is initiated at a power-on reset in user mode: 1 Mbyte
 The user boot memory MAT is initiated at a power-on reset in user boot mode: 8 kbytes
• Programming/erasing interface by the download of on-chip program
This LSI has a dedicated programming/erasing program. After downloading this program to
the on-chip RAM, programming/erasing can be performed by setting the argument parameter.
• Programming/erasing time
The flash memory programming time is 3 ms (typ) in 128-byte simultaneous programming,
and approximately 25 µs per byte. The erasing time is 1000 ms (typ) per 64-kbyte block.
• Number of programming
The number of flash memory programming can be up to 100 times at the minimum. (The value
ranged from 1 to 100 is guaranteed.)
• Three on-board programming modes
 Boot mode
This mode is a program mode that uses an on-chip SCI interface. The user MAT and user
boot MAT can be programmed. In this mode, the bit rate between the host and this LSI can
be automatically adjusted.
 User program mode
The user MAT can be programmed by using the optional interface.
ROM Size
R4F2114R 1 Mbyte
Section 21 Flash Memory (0.18-µm F-ZTAT Version)
ROM Addresses
H'000000 to H'0FFFFF (mode 2)
H'0000 to H'DFFF (mode 3)
Rev. 3.00 Jul. 14, 2005 Page 735 of 986
REJ09B0098-0300