Peripheral Clock Select Register (Pcsr) - Renesas H8S Series Hardware Manual

To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set
to port output.
DR data is output when the corresponding pin is used as port output. A value corresponding to
PWM 256/256 output is determined by the OS bit, so the value should have been set to DR
beforehand.
9.3.5

Peripheral Clock Select Register (PCSR)

PCSR selects the PWM input clock.
Bit Bit Name Initial Value

7 0

6 0
5 PWCKXB 0
4 PWCKXA 0

3 0
2 PWCKB 0
1 PWCKA 0
0 PWCKXC 0
R/W Description
R/W See section 10.3.4, Peripheral Clock Select Register
R/W (PCSR).
R/W
R/W
R/W
R/W PWM Clock Select B, A
R/W
Together with bits PWCKE and PWCKS in PWSL,
these bits select the internal clock input to the clock
counter in the PWM. For details, see table 9.2.
R/W See section 10.3.4, Peripheral Clock Select Register
(PCSR).
Section 9 8-Bit PWM Timer (PWM)
Rev. 3.00 Jul. 14, 2005 Page 253 of 986
REJ09B0098-0300