Renesas HD6417641 Manuals

Manuals and User Guides for Renesas HD6417641. We have 1 Renesas HD6417641 manual available for free PDF download: Hardware Manual

Renesas HD6417641 Hardware Manual (1036 pages)

32-Bit RISC Microcomputer SuperH RISC engine Family / SH7641 Series

Brand: Renesas | Category: Computer Hardware | Size: 6 MB

Keep Safety First in Your Circuit Designs
3
Notes Regarding These Materials
3
General Precautions on Handling of Product
4
Configuration of this Manual
6
Table of Contents
13
Section 1 Overview

51
- Features
  51
  - Table 1.1 Features
    51
  - Section 1 Overview
    52
  - Section 1 Overview
    53
- Block Diagram
  57
- Figure 1.1 Block Diagram
  57
- Pin Assignments
  58
- Figure 1.2 Pin Assignments (BGA-256)
  58
- Pin Functions
  59
- Table 1.2 Pin Functions
  59
- Table 1.3 Pin Functions
  59
Section 2 CPU

75
Section 3 DSP Operation

149
- Data Operations of DSP Unit
  149
- DSP Addressing
  174
Section 4 Clock Pulse Generator (CPG)

193
Section 5 Watchdog Timer (WDT)

205
- Features
  205
- Register Descriptions
  206
- Use of the WDT
  209
  - Canceling Standbys
    209
  - Figure 5.2 Writing to WTCNT and WTCSR
    209
  - Changing the Frequency
    210
  - Using Watchdog Timer Mode
    210
  - Using Interval Timer Mode
    211
- Precautions to Take When Using the WDT
  211
Section 6 Power-Down Modes

213
Section 7 Cache

229
- Features
  229
- Register Descriptions
  232
- Cache Operation
  236
  - Searching Cache
    236
  - Table 7.8 LRU and Way Replacement (When W2LOCK=1 and W3LOCK=1)
    236
  - Figure 7.2 Cache Search Scheme
    237
  - Read Access
    238
  - Prefetch Operation
    238
  - Write Access
    238
  - Write-Back Buffer
    239
  - Coherency of Cache and External Memory
    239
  - Figure 7.3 Write-Back Buffer Configuration
    239
- Memory-Mapped Cache
  240
  - Address Array
    240
  - Data Array
    240
  - Figure 7.4 Specifying Address and Data for Memory-Mapped Cache Access
    241
  - Usage Examples
    242
Section 8 X/Y Memory

243
- Features
  243
- X/Y Memory Access from CPU
  244
- X/Y Memory Access from DSP
  244
- Figure 8.1 X/Y Memory Address Mapping
  244
- X/Y Memory Access from DMAC
  245
- Usage Note
  245
- Sleep Mode
  245
- Address Error
  245
Section 9 Exception Handling

247
Section 10 Interrupt Controller (INTC)

269
- Features
  269
- Figure 10.1 Block Diagram of INTC
  270
- Input/Output Pins
  271
- Register Descriptions
  271
- Interrupt Sources
  283
  - NMI Interrupt
    283
  - H-UDI Interrupt
    283
  - IRQ Interrupts
    283
  - On-Chip Peripheral Module Interrupts
    284
  - Interrupt Exception Handling and Priority
    285
  - Table 10.5 Interrupt Exception Handling Sources and Priority
    286
- INTC Operation
  288
  - Interrupt Sequence
    288
  - Figure 10.2 Interrupt Operation Flowchart
    289
  - Multiple Interrupts
    290
- Notes on Use
  290
  - Notes on USB Bus Power Control
    290
  - Timing to Clear an Interrupt Source
    290
Section 11 User Break Controller (UBC)

291
- Features
  291
- Figure 11.1 Block Diagram of User Break Controller
  292
- Register Descriptions
  293
- Operation
  306
  - Flow of the User Break Operation
    306
  - Break on Instruction Fetch Cycle
    307
  - Break on Data Access Cycle
    308
  - Table 11.3 Data Access Cycle Addresses and Operand Size Comparison Conditions
    308
  - Break on X/Y-Memory Bus Cycle
    309
  - Sequential Break
    310
  - Value of Saved Program Counter
    310
  - PC Trace
    311
  - Usage Examples
    312
- Usage Notes
  316
Section 12 Bus State Controller (BSC)

319
Section 13 Direct Memory Access Controller (DMAC)

455
Section 14 U Memory

501
- Features
  501
- Table 14.1 U Memory Specifications
  501
- U Memory Access from CPU
  502
- U Memory Access from DSP
  502
- U Memory Access from DMAC
  502
- Figure 14.1 U Memory Address Mapping
  502
- Usage Note
  503
- Sleep Mode
  503
- Address Error
  503
Section 15 User Debugging Interface (H-UDI)

505
- Features
  505
- Figure 15.1 Block Diagram of H-UDI
  505
- Input/Output Pins
  506
- Table 15.1 Pin Configuration
  506
- Register Descriptions
  507
  - Bypass Register (SDBPR)
    507
  - Instruction Register (SDIR)
    507
  - Boundary Scan Register (SDBSR)
    508
  - Table 15.2 H-UDI Commands
    508
  - Table 15.3 this LSI Pins and Boundary Scan Register Bits
    509
  - ID Register (SDID)
    517
- Operation
  518
  - TAP Controller
    518
  - Figure 15.2 TAP Controller State Transitions
    518
  - Reset Configuration
    519
  - TDO Output Timing
    519
  - Table 15.4 Reset Configuration
    519
  - H-UDI Reset
    520
  - H-UDI Interrupt
    520
  - Figure 15.3 H-UDI Data Transfer Timing
    520
  - Figure 15.4 H-UDI Reset
    520
- Boundary Scan
  521
  - Supported Instructions
    521
  - Points for Attention
    522
- Usage Notes
  522
Section 16 I C Bus Interface 2 (IIC2)

523
Section 17 Compare Match Timer (CMT)

559
- Features
  559
- Figure 17.1 Block Diagram of Compare Match Timer
  559
- Register Descriptions
  560
- Operation
  563
  - Interval Count Operation
    563
  - CMCNT Count Timing
    563
  - Figure 17.2 Counter Operation
    563
  - Figure 17.3 Count Timing
    563
- Compare Matches
  564
Section 18 Multi-Function Timer Pulse Unit (MTU)

567
Section 19 Serial Communication Interface with FIFO (SCIF)

735
Section 20 USB Function Module

797
Section 21 A/D Converter

847
Section 22 Pin Function Controller (PFC)

869
- Table 22.1 List of Multiplexed Pins
  869
- Register Descriptions
  873
  - Port a Control Register (PACR)
    874
  - Port B Control Register (PBCR)
    876
  - Port C Control Register (PCCR)
    877
  - Port D Control Register (PDCR)
    878
  - Port E Control Register (PECR)
    880
  - Port E I/O Register (PEIOR)
    882
  - Port E MTU R/W Enable Register (PEMTURWER)
    883
  - Port F Control Register (PFCR)
    884
  - Port G Control Register
    886
  - Port H Control Register (PHCR)
    888
  - Port J Control Register (PJCR)
    889
- I/O Buffer Internal Block Diagram
  891
- Notes on Usage
  892
- Figure 22.2 Internal Block Diagram of I/O Buffer with Open Drain
  892
Section 23 I/O Ports

893
- Port a
  893
  - Register Description
    893
  - Figure 23.1 Port a
    893
  - Port a Data Register (PADR)
    894
- Port B
  895
- Port C
  897
  - Register Description
    897
  - Figure 23.3 Port C
    897
  - Port C Data Register (PCDR)
    898
- Port D
  899
- Port E
  901
- Port F
  903
- Port G
  906
- Port H
  910
  - Register Description
    910
  - Figure 23.9 Port H
    910
  - Port H Data Register (PHDR)
    911
- Port J
  912
Section 24 List of Registers

915
Section 25 Electrical Characteristics

957
Appendix

1017
- Pin States
  1017
  - When Other Function Is Selected
    1017
  - When I/O Port Is Selected
    1021
- Product Lineup
  1022
- Package Dimensions
  1023
- Figure C.1 Package Dimensions
  1023
Main Revisions and Additions in this Edition

1025
Index

1027

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Renesas HD6417641 Manuals

Renesas HD6417641 Hardware Manual (1036 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 DSP Operation

Section 4 Clock Pulse Generator (CPG)

Section 5 Watchdog Timer (WDT)

Section 6 Power-Down Modes

Section 7 Cache

Section 8 X/Y Memory

Section 9 Exception Handling

Section 10 Interrupt Controller (INTC)

Section 11 User Break Controller (UBC)

Section 12 Bus State Controller (BSC)

Section 13 Direct Memory Access Controller (DMAC)

Section 14 U Memory

Section 15 User Debugging Interface (H-UDI)

Section 16 I C Bus Interface 2 (IIC2)

Section 17 Compare Match Timer (CMT)

Section 18 Multi-Function Timer Pulse Unit (MTU)

Section 19 Serial Communication Interface with FIFO (SCIF)

Section 20 USB Function Module

Section 21 A/D Converter

Section 22 Pin Function Controller (PFC)

Section 23 I/O Ports

Section 24 List of Registers

Section 25 Electrical Characteristics

Appendix

Main Revisions and Additions in this Edition

Index

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