Bit Rate Register (Brr); Table 15.2 Relationships Between N Setting In Brr And Bit Rate B - Renesas H8S Series Hardware Manual

15.3.9

Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and
it can be read from or written to by the CPU at all times.

Table 15.2 Relationships between N Setting in BRR and Bit Rate B

Mode
Asynchronous mode
Clocked synchronous mode
Smart card interface mode
[Legend] B:
N:
φ:
n and S:
SMR Setting
CKS1
0
0
1
1
Bit Rate
B =
64 × 2
φ × 10
B =
2n – 1
8 × 2
B =
2n + 1
S × 2
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Determined by the SMR settings shown in the following table
CKS0 n
0 0
1 1
0 2
1 3
Section 15 Serial Communication Interface (SCI, IrDA)
φ × 10 6
2n – 1
× (N + 1)
6
× (N + 1)
φ × 10 6
× (N + 1)
SMR Setting
BCP1
0
0
1
1
Rev. 3.00 Jul. 14, 2005 Page 445 of 986
Error
φ × 10 6
Error (%) = {
2n – 1
B × 64 × 2 × (N + 1)

φ × 10 6
{
Error (%) =
2n + 1
B × S × 2 × (N + 1)
BCP0
0
1
0
1
REJ09B0098-0300
– 1 } × 100
}
–1 × 100
S
32
64
372
256