Module Stop Mode Setting; Operating Mode In Lpc/Fw Memory Write Cycle; Table 18.14 Host Address Example - Renesas H8S Series Hardware Manual

Table 18.14 Host Address Example

Register Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3FD0
IDR3 H'A24A and H'A24E
ODR3 H'A24A
STR3 H'A24E
TWR0MW H'A250
TWR0SW H'A250
TWR1 H'A251
TWR2 H'A252
TWR3 H'A253
TWR4 H'A254
TWR5 H'A255
TWR6 H'A256
TWR7 H'A257
TWR8 H'A258
TWR9 H'A259
TWR10 H'A25A
TWR11 H'A25B
TWR12 H'A25C
TWR13 H'A25D
TWR14 H'A25E
TWR15 H'A25F
18.6.2

Module Stop Mode Setting

Module stop mode should not be set to the LPC while the LPC/FW memory write cycle is
enabled. Specify module stop mode after confirming that the LMCE bit in LMCCR1 is cleared to
0.
18.6.3

Operating Mode in LPC/FW Memory Write Cycle

The LPC/FW memory cycle should be enabled in advanced mode; disabled in normal mode.
Section 18 LPC Interface (LPC)
H'3FD0 and H'3FD4
H'3FD0
H'3FD4
H'3FC0
H'3FC0
H'3FC1
H'3FC2
H'3FC3
H'3FC4
H'3FC5
H'3FC6
H'3FC7
H'3FC8
H'3FC9
H'3FCA
H'3FCB
H'3FCC
H'3FCD
H'3FCE
H'3FCF
Rev. 3.00 Jul. 14, 2005 Page 715 of 986
REJ09B0098-0300