Table 18.6 Scope Of Initialization In Each Lpc Interface Mode - Renesas H8S Series Hardware Manual

Table 18.6 Scope of Initialization in Each LPC interface Mode

Items Initialized
LPC transfer cycle sequencer (internal state), LPCBSY and ABRT
flags
SERIRQ transfer cycle sequencer (internal state), CLKREQ and
IRQBSY flags
LPC interface flags
(IBF1, IBF2, IBF3A, IBF3B, IBF4, MWMF, C/D1, C/D2, C/D3, C/D4,
OBF1, OBF2, OBF3A, OBF3B, OBF4, SWMF, DBU), GA20 (internal
state)
Host interrupt enable bits
(IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B,
SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3, SELREQ, SMIE4, IRQ6E4,
IRQ9E4 to IRQ11E4, IEDIR2 to IEDIR4), Q/C flag
LRST flag
SDWN flag
LRSTB bit
SDWNB bit
SDWNE bit
LPC interface operation control bits
(LPC4E to LPC1E, FGA20E, LADR4 to LADR1, IBFIE1 to IBFIE4,
PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB, TWRE, SELSTR3,
SELIRQ1, SELSMI, SELIRQ6, SELIRQ9 to SELIRQ12, HBAR1,
HBAR2, RAMBAR, SAR1, SAR2, RAMAR, ASSR, RAMASSR,
FWPRH, FWPRM, FWPRL, FRPRH, FRPRM, FRPRL, FLPI, FLEI,
BUFINII, USERI, FLPERR, FLEERR, PROTECT, LMCBUSY, LMCE,
LPCME, FWE, FLASHE, HDINIE, FLPIE, FLEIE, BUFINIIE, USERIE,
WAITSEL, MPCR, RBUFAR, FLWARH, FLWARL, LMCMIDCR,
LMCDIDCR, EBLKR, UCMDTR)
LPC interface operation control bits
ERASEE, WRITEE, RUFTRAN
Section 18 LPC Interface (LPC)
System
Reset LPC Reset
Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized (0) Can be
set/cleared
Initialized (0) Initialized (0) Can be
Initialized (0) HR: 0
SR: 1
Initialized (0) Initialized (0) HS: 0
Initialized (0) Initialized (0) HS: 1
Initialized Retained
Initialized Initialized
Rev. 3.00 Jul. 14, 2005 Page 685 of 986
REJ09B0098-0300
LPC
Shutdown
Initialized
Initialized
Retained
Retained
Can be
set/cleared
set/cleared
0 (can be
set)
SS: 1
SS: 0 or 1
Retained
Retained