Figure 18.1 Block Diagram Of Lpc - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Table of Contents

Figure 18.1 shows a block diagram of the LPC.

HICR0 to HICR4:

Host interface control registers 0 to 4

LADR3H, LADR3L:

LPC channel 3 address registers H and L

LADR4H, LADR4L:

LPC channel 4 address registers H and L

IDR1 to IDR4:

Input data registers 1 to 4

ODR1 to ODR4:

Output data registers 1 to 4

STR1 to STR4:

Status registers 1 to 4

Module data bus

Cycle detection

Serial → parallel conversion

Address match

Serial ← parallel conversion

Figure 18.1 Block Diagram of LPC

Parallel → serial conversion

Control logic

LPC/FW memory

cycle set register

Internal interrupt

Bidirectional data register 0MW

Bidirectional data register 0SW

TWR15: Bidirectional data registers 1 to 15

SERIRQ0 to SERIRQ2:

SERIEQ control registers 0 to 2

Host interface select register

Port control register 2

Rev. 3.00 Jul. 14, 2005 Page 615 of 986

Section 18 LPC Interface (LPC)

REJ09B0098-0300

H8s/2100 series H8s/2114r R4f2114r